clk: meson: meson8b: add the cts_amclk clocks

Add the I2S master clock also referred as cts_amclk. The setup for this
clock is identical to GXBB, so this ports commit 4087bd4b21702d ("clk:
meson: gxbb: add cts_amclk") to the Meson8/Meson8b/Meson8m2 clock
driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 62cd3a7..e00f42e 100644 (file)
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -2153,6 +2153,59 @@ static struct clk_regmap meson8b_vdec_hevc = {
        },
 };
 
+/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
+static const char * const meson8b_cts_amclk_parent_names[] = {
+       "mpll0", "mpll1", "mpll2"
+};
+
+static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
+
+static struct clk_regmap meson8b_cts_amclk_sel = {
+       .data = &(struct clk_regmap_mux_data){
+               .offset = HHI_AUD_CLK_CNTL,
+               .mask = 0x3,
+               .shift = 9,
+               .table = meson8b_cts_amclk_mux_table,
+               .flags = CLK_MUX_ROUND_CLOSEST,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "cts_amclk_sel",
+               .ops = &clk_regmap_mux_ops,
+               .parent_names = meson8b_cts_amclk_parent_names,
+               .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_names),
+       },
+};
+
+static struct clk_regmap meson8b_cts_amclk_div = {
+       .data = &(struct clk_regmap_div_data) {
+               .offset = HHI_AUD_CLK_CNTL,
+               .shift = 0,
+               .width = 8,
+               .flags = CLK_DIVIDER_ROUND_CLOSEST,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "cts_amclk_div",
+               .ops = &clk_regmap_divider_ops,
+               .parent_names = (const char *[]){ "cts_amclk_sel" },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
+static struct clk_regmap meson8b_cts_amclk = {
+       .data = &(struct clk_regmap_gate_data){
+               .offset = HHI_AUD_CLK_CNTL,
+               .bit_idx = 8,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "cts_amclk",
+               .ops = &clk_regmap_gate_ops,
+               .parent_names = (const char *[]){ "cts_amclk_div" },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
 /* Everything Else (EE) domain gates */
 
 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -2432,6 +2485,9 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
                [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
                [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
                [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
+               [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
+               [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
+               [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
                [CLK_NR_CLKS]               = NULL,
        },
        .num = CLK_NR_CLKS,
@@ -2641,6 +2697,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
                [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
                [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
                [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
+               [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
+               [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
+               [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
                [CLK_NR_CLKS]               = NULL,
        },
        .num = CLK_NR_CLKS,
@@ -2852,6 +2911,9 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
                [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
                [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
                [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
+               [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
+               [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
+               [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
                [CLK_NR_CLKS]               = NULL,
        },
        .num = CLK_NR_CLKS,
@@ -3041,6 +3103,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
        &meson8b_vdec_hevc_div,
        &meson8b_vdec_hevc_en,
        &meson8b_vdec_hevc,
+       &meson8b_cts_amclk,
+       &meson8b_cts_amclk_sel,
+       &meson8b_cts_amclk_div,
 };
 
 static const struct meson8b_clk_reset_line {

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index ed37196..03efa47 100644 (file)
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -30,6 +30,7 @@
 #define HHI_SYS_CPU_CLK_CNTL1          0x15c /* 0x57 offset in data sheet */
 #define HHI_VID_CLK_DIV                        0x164 /* 0x59 offset in data sheet */
 #define HHI_MPEG_CLK_CNTL              0x174 /* 0x5d offset in data sheet */
+#define HHI_AUD_CLK_CNTL               0x178 /* 0x5e offset in data sheet */
 #define HHI_VID_CLK_CNTL               0x17c /* 0x5f offset in data sheet */
 #define HHI_VID_CLK_CNTL2              0x194 /* 0x65 offset in data sheet */
 #define HHI_VID_DIVIDER_CNTL           0x198 /* 0x66 offset in data sheet */
@@ -171,8 +172,10 @@
 #define CLKID_VDEC_HEVC_SEL    203
 #define CLKID_VDEC_HEVC_DIV    204
 #define CLKID_VDEC_HEVC_EN     205
+#define CLKID_CTS_AMCLK_SEL    207
+#define CLKID_CTS_AMCLK_DIV    208
 
-#define CLK_NR_CLKS            207
+#define CLK_NR_CLKS            210
 
 /*
  * include the CLKID and RESETID that have