x86: coreboot: Control I/O port 0xb2 writing via device tree
authorBin Meng <bmeng.cn@gmail.com>
Wed, 3 Jun 2015 01:20:05 +0000 (09:20 +0800)
committerSimon Glass <sjg@chromium.org>
Thu, 4 Jun 2015 09:03:18 +0000 (03:03 -0600)
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/coreboot/coreboot.c
arch/x86/dts/qemu-x86_q35.dts

index c3dfd28..c4cac04 100644 (file)
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/msr.h>
@@ -74,9 +75,14 @@ void board_final_cleanup(void)
                mtrr_close(&state);
        }
 
-       /* Issue SMI to Coreboot to lock down ME and registers */
-       printf("Finalizing Coreboot\n");
-       outb(0xcb, 0xb2);
+       if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
+               /*
+                * Issue SMI to coreboot to lock down ME and registers
+                * when allowed via device tree
+                */
+               printf("Finalizing coreboot\n");
+               outb(0xcb, 0xb2);
+       }
 }
 
 int misc_init_r(void)
index 6c89283..02a483c 100644 (file)
@@ -15,6 +15,7 @@
 
        config {
                silent_console = <0>;
+               u-boot,no-apm-finalize;
        };
 
        chosen {