rtw88: fix RX clock gate setting while fifo dump

[ Upstream commit c5a8e90730a322f236731fc347dd3afa5db5550e ]

When fw fifo dumps, RX clock gating should be disabled to avoid
something unexpected. However, the register operation ran into
a mistake. So, we fix it.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20210927111830.5354-1-pkshih@realtek.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/wireless/realtek/rtw88/fw.c b/drivers/net/wireless/realtek/rtw88/fw.c
index e639951..a384fc3 100644 (file)
--- a/drivers/net/wireless/realtek/rtw88/fw.c
+++ b/drivers/net/wireless/realtek/rtw88/fw.c
@@ -1556,12 +1556,10 @@ static void rtw_fw_read_fifo_page(struct rtw_dev *rtwdev, u32 offset, u32 size,
        u32 i;
        u16 idx = 0;
        u16 ctl;
-       u8 rcr;
 
-       rcr = rtw_read8(rtwdev, REG_RCR + 2);
        ctl = rtw_read16(rtwdev, REG_PKTBUF_DBG_CTRL) & 0xf000;
        /* disable rx clock gate */
-       rtw_write8(rtwdev, REG_RCR, rcr | BIT(3));
+       rtw_write32_set(rtwdev, REG_RCR, BIT_DISGCLK);
 
        do {
                rtw_write16(rtwdev, REG_PKTBUF_DBG_CTRL, start_pg | ctl);
@@ -1580,7 +1578,8 @@ static void rtw_fw_read_fifo_page(struct rtw_dev *rtwdev, u32 offset, u32 size,
 
 out:
        rtw_write16(rtwdev, REG_PKTBUF_DBG_CTRL, ctl);
-       rtw_write8(rtwdev, REG_RCR + 2, rcr);
+       /* restore rx clock gate */
+       rtw_write32_clr(rtwdev, REG_RCR, BIT_DISGCLK);
 }
 
 static void rtw_fw_read_fifo(struct rtw_dev *rtwdev, enum rtw_fw_fifo_sel sel,

diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h
index f5ce750..c0fb1e4 100644 (file)
--- a/drivers/net/wireless/realtek/rtw88/reg.h
+++ b/drivers/net/wireless/realtek/rtw88/reg.h
@@ -406,6 +406,7 @@
 #define BIT_MFBEN              BIT(22)
 #define BIT_DISCHKPPDLLEN      BIT(21)
 #define BIT_PKTCTL_DLEN                BIT(20)
+#define BIT_DISGCLK            BIT(19)
 #define BIT_TIM_PARSER_EN      BIT(18)
 #define BIT_BC_MD_EN           BIT(17)
 #define BIT_UC_MD_EN           BIT(16)