Handle invalid prefixes for rdrand and rdseed

This patch puts rdrand and rdseed in prefix_table so that invalid
prefixes for rdrand and rdseed are handled properly.

gas/testsuite/

	PR binutils/17898
	* gas/i386/prefix.s: Add rdrand/rdseed prefix tests.
	* gas/i386/prefix.d: Updated.

opcodes/

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index ea6a87a..5fa02ac 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR binutils/17898
+       * gas/i386/prefix.s: Add rdrand/rdseed prefix tests.
+       * gas/i386/prefix.d: Updated.
+
 2015-04-15  Renlin Li  <renlin.li@arm.com>
 
        * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.

diff --git a/gas/testsuite/gas/i386/prefix.d b/gas/testsuite/gas/i386/prefix.d
index a334ab8..7afb0c1 100644 (file)
--- a/gas/testsuite/gas/i386/prefix.d
+++ b/gas/testsuite/gas/i386/prefix.d
@@ -63,4 +63,15 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f3 f0 66 3e 36 90       lock data16 ds ss pause 
 [      ]*[a-f0-9]+:    f3 f2 67 3e 36 90       repz repnz addr16 ds ss nop
 [      ]*[a-f0-9]+:    f3 67 f2 66 3e 36 90    repz addr16 repnz ds ss xchg %ax,%ax
+[      ]*[a-f0-9]+:    f3 0f c7                \(bad\)  
+[      ]*[a-f0-9]+:    f8                      clc    
+[      ]*[a-f0-9]+:    90                      nop
+[      ]*[a-f0-9]+:    f3 0f c7                \(bad\)  
+[      ]*[a-f0-9]+:    f0 90                   lock nop
+[      ]*[a-f0-9]+:    f2 0f c7                \(bad\)  
+[      ]*[a-f0-9]+:    f8                      clc    
+[      ]*[a-f0-9]+:    90                      nop
+[      ]*[a-f0-9]+:    f2 0f c7                \(bad\)  
+[      ]*[a-f0-9]+:    f0 90                   lock nop
+       ...
 #pass

diff --git a/gas/testsuite/gas/i386/prefix.s b/gas/testsuite/gas/i386/prefix.s
index 9f90afa..12d8bbc 100644 (file)
--- a/gas/testsuite/gas/i386/prefix.s
+++ b/gas/testsuite/gas/i386/prefix.s
@@ -359,5 +359,37 @@
        .byte 0x36
        .byte 0x90
 
+# repz; rdseed %eax
+       .byte 0xf3
+       .byte 0x0f
+       .byte 0xc7
+       .byte 0xf8
+
+       nop
+
+# repz; rdrand %eax
+       .byte 0xf3
+       .byte 0x0f
+       .byte 0xc7
+       .byte 0xf0
+
+       nop
+
+# repnz; rdseed %eax
+       .byte 0xf2
+       .byte 0x0f
+       .byte 0xc7
+       .byte 0xf8
+
+       nop
+
+# repnz; rdrand %eax
+       .byte 0xf2
+       .byte 0x0f
+       .byte 0xc7
+       .byte 0xf0
+
+       nop
+
 # Get a good alignment.
  .p2align      4,0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b378dc1..b46c861 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,19 @@
 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 
+       PR binutils/17898
+       * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
+       (PREFIX_MOD_0_0FC7_REG_6): This.
+       (PREFIX_MOD_3_0FC7_REG_6): New.
+       (PREFIX_MOD_3_0FC7_REG_7): Likewise.
+       (prefix_table): Replace PREFIX_0FC7_REG_6 with
+       PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
+       PREFIX_MOD_3_0FC7_REG_7.
+       (mod_table): Replace PREFIX_0FC7_REG_6 with
+       PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
+       PREFIX_MOD_3_0FC7_REG_7.
+
+2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
+
        * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
        (PREFIX_MANDATORY_REPNZ): Likewise.
        (PREFIX_MANDATORY_DATA): Likewise.

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 1841488..76ecb5a 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -933,7 +933,9 @@ enum
   PREFIX_0FBD,
   PREFIX_0FC2,
   PREFIX_0FC3,
-  PREFIX_0FC7_REG_6,
+  PREFIX_MOD_0_0FC7_REG_6,
+  PREFIX_MOD_3_0FC7_REG_6,
+  PREFIX_MOD_3_0FC7_REG_7,
   PREFIX_0FD0,
   PREFIX_0FD6,
   PREFIX_0FE6,
@@ -4047,13 +4049,27 @@ static const struct dis386 prefix_table[][4] = {
     { "movntiS", { Ma, Gv }, PREFIX_OPCODE },
   },
 
-  /* PREFIX_0FC7_REG_6 */
+  /* PREFIX_MOD_0_0FC7_REG_6 */
   {
     { "vmptrld",{ Mq }, 0 },
     { "vmxon", { Mq }, 0 },
     { "vmclear",{ Mq }, 0 },
   },
 
+  /* PREFIX_MOD_3_0FC7_REG_6 */
+  {
+    { "rdrand",        { Ev }, 0 },
+    { Bad_Opcode },
+    { "rdrand",        { Ev }, 0 }
+  },
+
+  /* PREFIX_MOD_3_0FC7_REG_7 */
+  {
+    { "rdseed",        { Ev }, 0 },
+    { Bad_Opcode },
+    { "rdseed",        { Ev }, 0 },
+  },
+
   /* PREFIX_0FD0 */
   {
     { Bad_Opcode },
@@ -11808,13 +11824,13 @@ static const struct dis386 mod_table[][2] = {
   },
   {
     /* MOD_0FC7_REG_6 */
-    { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
-    { "rdrand",                { Ev }, 0 },
+    { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
+    { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
   },
   {
     /* MOD_0FC7_REG_7 */
     { "vmptrst",       { Mq }, 0 },
-    { "rdseed",                { Ev }, 0 },
+    { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
   },
   {
     /* MOD_0FD7 */