radv: Add option to disable DCC in renderpasses without layout.

If DCC is enabled for GENERAL then we cannot disable DCC by going
to the GENERAL layout.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7004>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 15e9b1e..2b0453e 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1609,7 +1609,8 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
                         struct radv_color_buffer_info *cb,
                         struct radv_image_view *iview,
                         VkImageLayout layout,
-                        bool in_render_loop)
+                        bool in_render_loop,
+                        bool disable_dcc)
 {
        bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
        uint32_t cb_color_info = cb->cb_color_info;
@@ -1618,7 +1619,8 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
        if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
                                        radv_image_queue_family_mask(image,
                                                                     cmd_buffer->queue_family_index,
-                                                                    cmd_buffer->queue_family_index))) {
+                                                                    cmd_buffer->queue_family_index)) ||
+           disable_dcc) {
                cb_color_info &= C_028C70_DCC_ENABLE;
        }
 
@@ -2385,7 +2387,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
 
                assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
                                                       VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
-               radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
+               radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout,
+                                        in_render_loop, cmd_buffer->state.attachments[idx].disable_dcc);
 
                radv_load_color_clear_metadata(cmd_buffer, iview, i);
        }
@@ -3634,7 +3637,8 @@ radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
 static VkResult
 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
                                 struct radv_render_pass *pass,
-                                const VkRenderPassBeginInfo *info)
+                                const VkRenderPassBeginInfo *info,
+                                const struct radv_extra_render_pass_begin_info *extra)
 {
        struct radv_cmd_state *state = &cmd_buffer->state;
        const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
@@ -3694,6 +3698,7 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
                state->attachments[i].current_layout = att->initial_layout;
                state->attachments[i].current_in_render_loop = false;
                state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
+               state->attachments[i].disable_dcc = extra && extra->disable_dcc;
                state->attachments[i].sample_location.count = 0;
 
                struct radv_image_view *iview;
@@ -3831,7 +3836,7 @@ VkResult radv_BeginCommandBuffer(
                        &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
 
                if (cmd_buffer->state.framebuffer) {
-                       result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
+                       result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL, NULL);
                        if (result != VK_SUCCESS)
                                return result;
                }
@@ -5051,7 +5056,8 @@ radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
 
 void
 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
-                                 const VkRenderPassBeginInfo *pRenderPassBegin)
+                                 const VkRenderPassBeginInfo *pRenderPassBegin,
+                                 const struct radv_extra_render_pass_begin_info *extra_info)
 {
        RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
        RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
@@ -5061,7 +5067,7 @@ radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
        cmd_buffer->state.pass = pass;
        cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
 
-       result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
+       result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin, extra_info);
        if (result != VK_SUCCESS)
                return;
 
@@ -5077,7 +5083,7 @@ void radv_CmdBeginRenderPass(
 {
        RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 
-       radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
+       radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin, NULL);
 
        radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
 }

diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index 287ff24..f2aa9d8 100644 (file)
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -323,7 +323,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
                                                                },
                                                        .clearValueCount = 0,
                                                        .pClearValues = NULL,
-                                               });
+                                               }, NULL);
                switch (src_image->type) {
                case VK_IMAGE_TYPE_1D:
                        pipeline = &device->meta_state.blit.pipeline_1d_src[fs_key];
@@ -352,7 +352,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
                                                        },
                                                        .clearValueCount = 0,
                                                        .pClearValues = NULL,
-                                                 });
+                                                 }, NULL);
                switch (src_image->type) {
                case VK_IMAGE_TYPE_1D:
                        pipeline = &device->meta_state.blit.depth_only_1d_pipeline;
@@ -381,7 +381,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
                                                        },
                                                        .clearValueCount = 0,
                                                        .pClearValues = NULL,
-                                                 });
+                                                 }, NULL);
                switch (src_image->type) {
                case VK_IMAGE_TYPE_1D:
                        pipeline = &device->meta_state.blit.stencil_only_1d_pipeline;

diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c
index 74aaaaa..22d9dd2 100644 (file)
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -310,7 +310,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
                                                                        },
                                                                        .clearValueCount = 0,
                                                                        .pClearValues = NULL,
-                                                                 });
+                                                                 }, NULL);
 
                                radv_cmd_buffer_set_subpass(cmd_buffer,
                                                            &cmd_buffer->state.pass->subpasses[0]);
@@ -338,7 +338,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
                                                                        },
                                                                        .clearValueCount = 0,
                                                                        .pClearValues = NULL,
-                                                                 });
+                                                                 }, NULL);
 
                                radv_cmd_buffer_set_subpass(cmd_buffer,
                                                            &cmd_buffer->state.pass->subpasses[0]);
@@ -367,7 +367,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
                                                                        },
                                                                        .clearValueCount = 0,
                                                                        .pClearValues = NULL,
-                                                                  });
+                                                                  }, NULL);
 
                                radv_cmd_buffer_set_subpass(cmd_buffer,
                                                            &cmd_buffer->state.pass->subpasses[0]);

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 63da45c..a3724d6 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -2095,7 +2095,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
                                                .framebuffer = fb,
                                                .clearValueCount = 0,
                                                .pClearValues = NULL,
-                                        });
+                                        }, NULL);
 
        radv_cmd_buffer_set_subpass(cmd_buffer,
                                    &cmd_buffer->state.pass->subpasses[0]);

diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c
index 1de57bf..4ac3c25 100644 (file)
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -460,7 +460,7 @@ radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer,
                                                },
                                                .clearValueCount = 0,
                                                .pClearValues = NULL,
-                                       });
+                                       }, NULL);
        radv_cmd_buffer_set_subpass(cmd_buffer,
                                    &cmd_buffer->state.pass->subpasses[0]);
 

diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index 310e48c..87c2f92 100644 (file)
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -631,7 +631,7 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer,
                                                },
                                                .clearValueCount = 0,
                                                .pClearValues = NULL,
-                                       });
+                                       }, NULL);
 
        radv_cmd_buffer_set_subpass(cmd_buffer,
                                    &cmd_buffer->state.pass->subpasses[0]);

diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index 42d1347..8ed3f40 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -571,7 +571,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer,
                                                        },
                                                        .clearValueCount = 0,
                                                        .pClearValues = NULL,
-                                             });
+                                             }, NULL);
 
                radv_cmd_buffer_set_subpass(cmd_buffer,
                                            &cmd_buffer->state.pass->subpasses[0]);

diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c
index 4ba30de..6fc1901 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -1098,7 +1098,7 @@ void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
                                                                },
                                                        .clearValueCount = 0,
                                                        .pClearValues = NULL,
-                                       });
+                                       }, NULL);
 
                radv_cmd_buffer_set_subpass(cmd_buffer,
                                            &cmd_buffer->state.pass->subpasses[0]);

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index d0146d8..9dec177 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1291,6 +1291,7 @@ struct radv_attachment_state {
        VkImageLayout                                current_layout;
        VkImageLayout                                current_stencil_layout;
        bool                                         current_in_render_loop;
+       bool                                         disable_dcc;
        struct radv_sample_locations_state           sample_location;
 
        union {
@@ -2628,8 +2629,14 @@ si_conv_gl_prim_to_vertices(unsigned gl_prim)
        }
 }
 
+
+struct radv_extra_render_pass_begin_info {
+       bool disable_dcc;
+};
+
 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
-                                      const VkRenderPassBeginInfo *pRenderPassBegin);
+                                      const VkRenderPassBeginInfo *pRenderPassBegin,
+                                      const struct radv_extra_render_pass_begin_info *extra_info);
 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
 
 static inline uint32_t si_translate_prim(unsigned topology)