defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr">;
defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv">;
- defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd">;
- defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub">;
- defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul">;
- defm FTSMUL_ZZZ : sve_fp_3op_u_zd<0b011, "ftsmul">;
- defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps">;
- defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts">;
+ defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd", fadd>;
+ defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub", null_frag>;
+ defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul", null_frag>;
+ defm FTSMUL_ZZZ : sve_fp_3op_u_zd<0b011, "ftsmul", null_frag>;
+ defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps", null_frag>;
+ defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts", null_frag>;
defm FTSSEL_ZZZ : sve_int_bin_cons_misc_0_b<"ftssel">;
//===----------------------------------------------------------------------===//
class sve_fp_3op_u_zd<bits<2> sz, bits<3> opc, string asm,
- ZPRRegOp zprty>
+ ZPRRegOp zprty,
+ ValueType vt, ValueType vt2, SDPatternOperator op>
: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
asm, "\t$Zd, $Zn, $Zm",
- "", []>, Sched<[]> {
+ "",
+ [(set (vt zprty:$Zd), (op (vt zprty:$Zn), (vt2 zprty:$Zm)))]>, Sched<[]> {
bits<5> Zd;
bits<5> Zm;
bits<5> Zn;
let Inst{4-0} = Zd;
}
-multiclass sve_fp_3op_u_zd<bits<3> opc, string asm> {
- def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>;
- def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>;
- def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64>;
+multiclass sve_fp_3op_u_zd<bits<3> opc, string asm, SDPatternOperator op> {
+ def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16, nxv8f16, nxv8f16, op>;
+ def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32, nxv4f32, nxv4f32, op>;
+ def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64, nxv2f64, nxv2f64, op>;
}
//===----------------------------------------------------------------------===//
--- /dev/null
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 8 x half> @fadd_h(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: fadd_h:
+; CHECK: fadd z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+ %res = fadd <vscale x 8 x half> %a, %b
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x float> @fadd_s(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: fadd_s:
+; CHECK: fadd z0.s, z0.s, z1.s
+; CHECK-NEXT: ret
+ %res = fadd <vscale x 4 x float> %a, %b
+ ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x double> @fadd_d(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: fadd_d:
+; CHECK: fadd z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+ %res = fadd <vscale x 2 x double> %a, %b
+ ret <vscale x 2 x double> %res
+}