riscv:linux:drm:

update code after pll switch to 1188m
based on new pll config, fix rgb bug caused by old pll

Signed-off-by: shengyang.chen<shengyang.chen@starfivetech.com>

diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c
index c1e88c4..53fbe52 100755 (executable)
--- a/drivers/gpu/drm/verisilicon/vs_dc.c
+++ b/drivers/gpu/drm/verisilicon/vs_dc.c
@@ -806,12 +806,21 @@ static void vs_dc_enable(struct device *dev, struct drm_crtc *crtc)
        display.enable = true;
 
        if (crtc_state->encoder_type == DRM_MODE_ENCODER_DSI){
-               clk_set_rate(dc->dc8200_pix0, mode->clock*1000);
-               clk_set_parent(dc->dc8200_clk_pix1, dc->dc8200_pix0);
+               if (dc->pix_clk_rate != mode->clock) {
+                       clk_set_rate(dc->dc8200_pix0, mode->clock * 1000);
+                       dc->pix_clk_rate = mode->clock;
+               }
+
+               clk_set_parent(dc->dc8200_clk_pix1, dc->dc8200_pix0 );//child,parent
                udelay(1000);
                dc_hw_set_out(&dc->hw, OUT_DPI, display.id);
-       }else{
-               clk_set_parent(dc->dc8200_clk_pix1, dc->hdmitx0_pixelclk);
+       } else {
+               if (dc->pix_clk_rate != mode->clock) {
+                       clk_set_rate(dc->dc8200_pix0, mode->clock * 1000);
+                       dc->pix_clk_rate = mode->clock;
+               }
+
+               clk_set_parent(dc->dc8200_clk_pix1, dc->dc8200_pix0);
                clk_set_parent(dc->dc8200_clk_pix0, dc->hdmitx0_pixelclk);
                dc_hw_set_out(&dc->hw, OUT_DP, display.id);
        }