MIPS: Use Ingenic-specific write combine attribute on all Ingenic platforms
authorAlex Smith <alex.smith@imgtec.com>
Fri, 24 Jul 2015 15:16:12 +0000 (16:16 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 3 Sep 2015 10:08:01 +0000 (12:08 +0200)
The Ingenic-specific write combining cache attribute was defined based
on CONFIG_MACH_JZ4740 and therefore not used on JZ4780. Change this to
CONFIG_MACH_INGENIC so that it gets used on all Ingenic platforms.

Signed-off-by: Alex Smith <alex.smith@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10769/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/pgtable-bits.h

index c28a849..002eeb2 100644 (file)
@@ -249,7 +249,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
 #define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
 
-#elif defined(CONFIG_MACH_JZ4740)
+#elif defined(CONFIG_MACH_INGENIC)
 
 /* Ingenic uses the WA bit to achieve write-combine memory writes */
 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)