add support for plane instruction (pln)

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

diff --git a/assembler/src/brw_defines.h b/assembler/src/brw_defines.h
index 4921d34..7e8650a 100644 (file)
--- a/assembler/src/brw_defines.h
+++ b/assembler/src/brw_defines.h
@@ -603,6 +603,7 @@
 #define BRW_OPCODE_DP2        87
 #define BRW_OPCODE_DPA2       88
 #define BRW_OPCODE_LINE       89
+#define BRW_OPCODE_PLN        90
 #define BRW_OPCODE_NOP        126
 
 #define BRW_PREDICATE_NONE                   0

diff --git a/assembler/src/gram.y b/assembler/src/gram.y
index 93912c2..d50e6fa 100644 (file)
--- a/assembler/src/gram.y
+++ b/assembler/src/gram.y
@@ -101,7 +101,7 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
 
 %token <integer> MOV FRC RNDU RNDD RNDE RNDZ NOT LZD
 %token <integer> MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2
-%token <integer> AVG ADD SEL AND OR XOR SHR SHL ASR CMP CMPN
+%token <integer> AVG ADD SEL AND OR XOR SHR SHL ASR CMP CMPN PLN
 %token <integer> SEND NOP JMPI IF IFF WHILE ELSE BREAK CONT HALT MSAVE
 %token <integer> PUSH MREST POP WAIT DO ENDIF ILLEGAL
 
@@ -301,7 +301,7 @@ binaryaccinstruction:
                }
 ;
 
-binaryaccop:   AVG | ADD | SEL | AND | OR | XOR | SHR | SHL | ASR | CMP | CMPN
+binaryaccop:   AVG | ADD | SEL | AND | OR | XOR | SHR | SHL | ASR | CMP | CMPN | PLN
 ;
 
 triinstruction:        sendinstruction

diff --git a/assembler/src/lex.l b/assembler/src/lex.l
index ead12af..482d68e 100644 (file)
--- a/assembler/src/lex.l
+++ b/assembler/src/lex.l
@@ -96,6 +96,8 @@ extern char *input_filename;
 "do" { yylval.integer = BRW_OPCODE_DO; return DO; }
 "endif" { yylval.integer = BRW_OPCODE_ENDIF; return ENDIF; }
 
+"pln" { yylval.integer = BRW_OPCODE_PLN; return PLN; }
+
  /* send argument tokens */
 "mlen" { return MSGLEN; }
 "rlen" { return RETURNLEN; }