intel/nir: temporarly disable opt_uniform_atomics for RT/CL

Not had time to investiguate what is going is on but it's definitely a
contributor to failures.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16104>

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 87fff7c..9ceb627 100644 (file)
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -1236,8 +1236,17 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
 
    /* TODO: Enable nir_opt_uniform_atomics on Gfx7.x too.
     * It currently fails Vulkan tests on Haswell for an unknown reason.
+    *
+    * TODO: Using this optimization on RT/OpenCL kernels also seems to cause
+    *       issues. Until we can understand those issues, disable it.
     */
-   if (devinfo->ver >= 8 && OPT(nir_opt_uniform_atomics)) {
+   bool opt_uniform_atomic_stage_allowed =
+      devinfo->ver >= 8 &&
+      nir->info.stage != MESA_SHADER_KERNEL &&
+      nir->info.stage != MESA_SHADER_RAYGEN &&
+      !gl_shader_stage_is_callable(nir->info.stage);
+
+   if (opt_uniform_atomic_stage_allowed && OPT(nir_opt_uniform_atomics)) {
       const nir_lower_subgroups_options subgroups_options = {
          .ballot_bit_size = 32,
          .ballot_components = 1,