cxl/regs: Remove early capability checks in Component Register setup

When probing the Component Registers in function cxl_probe_regs()
there are also checks for the existence of the HDM and RAS
capabilities. The checks may fail for components that do not implement
the HDM capability causing the Component Registers setup to fail too.

Remove the checks for a generalized use of cxl_probe_regs() and check
them directly before mapping the RAS or HDM capabilities. This allows
it to setup other Component Registers esp. of an RCH Downstream Port,
which will be implemented in a follow-on patch.

Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-12-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index e035ad8..e688480 100644 (file)
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -369,14 +369,6 @@ static int cxl_probe_regs(struct cxl_register_map *map)
        case CXL_REGLOC_RBI_COMPONENT:
                comp_map = &map->component_map;
                cxl_probe_component_regs(dev, base, comp_map);
-               if (!comp_map->hdm_decoder.valid) {
-                       dev_err(dev, "HDM decoder registers not found\n");
-                       return -ENXIO;
-               }
-
-               if (!comp_map->ras.valid)
-                       dev_dbg(dev, "RAS registers not found\n");
-
                dev_dbg(dev, "Set up component registers\n");
                break;
        case CXL_REGLOC_RBI_MEMDEV:

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index ac17bc0..945ca03 100644 (file)
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -630,6 +630,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
        if (rc)
                dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
+       else if (!map.component_map.ras.valid)
+               dev_dbg(&pdev->dev, "RAS registers not found\n");
 
        cxlds->component_reg_phys = map.resource;
 

diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 4cef2bf..01e84ea 100644 (file)
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -102,8 +102,11 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
                return rc;
 
        cxlhdm = devm_cxl_setup_hdm(port, &info);
-       if (IS_ERR(cxlhdm))
+       if (IS_ERR(cxlhdm)) {
+               if (PTR_ERR(cxlhdm) == -ENODEV)
+                       dev_err(&port->dev, "HDM decoder registers not found\n");
                return PTR_ERR(cxlhdm);
+       }
 
        /* Cache the data early to ensure is_visible() works */
        read_cdat_data(port);