bool Selected = false;
// Register information
bool TracksRegLiveness = false;
- bool TracksSubRegLiveness = false;
std::vector<VirtualRegisterDefinition> VirtualRegisters;
std::vector<MachineFunctionLiveIn> LiveIns;
Optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
YamlIO.mapOptional("selected", MF.Selected);
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
- YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
YamlIO.mapOptional("registers", MF.VirtualRegisters);
YamlIO.mapOptional("liveins", MF.LiveIns);
YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);
Delegate *TheDelegate;
/// True if subregister liveness is tracked.
- bool TracksSubRegLiveness;
+ const bool TracksSubRegLiveness;
/// VRegInfo - Information we keep for each virtual register.
///
return TracksSubRegLiveness;
}
- void enableSubRegLiveness(bool Enable = true) {
- TracksSubRegLiveness = Enable;
- }
-
//===--------------------------------------------------------------------===//
// Register Info
//===--------------------------------------------------------------------===//
}
/// Enable tracking of subregister liveness in register allocator.
+ /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
+ /// possible.
virtual bool enableSubRegLiveness() const { return false; }
};
// register coalescer cannot deal with hidden dead defs. However without
// subregister liveness enabled, the expected benefits of this pass are small
// so we safe the compile time.
- if (!MF.getSubtarget().enableSubRegLiveness()) {
+ MRI = &MF.getRegInfo();
+ if (!MRI->subRegLivenessEnabled()) {
DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
return false;
}
- MRI = &MF.getRegInfo();
TRI = MRI->getTargetRegisterInfo();
unsigned NumVirtRegs = MRI->getNumVirtRegs();
static bool EnablePrecomputePhysRegs = false;
#endif // NDEBUG
-static cl::opt<bool> EnableSubRegLiveness(
- "enable-subreg-liveness", cl::Hidden, cl::init(true),
- cl::desc("Enable subregister liveness tracking."));
-
namespace llvm {
cl::opt<bool> UseSegmentSetForPhysRegs(
"use-segment-set-for-physregs", cl::Hidden, cl::init(true),
Indexes = &getAnalysis<SlotIndexes>();
DomTree = &getAnalysis<MachineDominatorTree>();
- if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
- MRI->enableSubRegLiveness(true);
-
if (!LRCalc)
LRCalc = new LiveRangeCalc();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
RegInfo.invalidateLiveness();
- RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
SMDiagnostic Error;
// Parse the virtual register information.
const MachineRegisterInfo &RegInfo,
const TargetRegisterInfo *TRI) {
MF.TracksRegLiveness = RegInfo.tracksLiveness();
- MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
// Print the virtual register definitions.
for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
using namespace llvm;
+static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
+ cl::init(true), cl::desc("Enable subregister liveness tracking."));
+
// Pin the vtable to this file.
void MachineRegisterInfo::Delegate::anchor() {}
MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
- : MF(MF), TheDelegate(nullptr), TracksSubRegLiveness(false) {
+ : MF(MF), TheDelegate(nullptr),
+ TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
+ EnableSubRegLiveness) {
unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
bool RenameIndependentSubregs::runOnMachineFunction(MachineFunction &MF) {
// Skip renaming if liveness of subregister is not tracked.
- if (!MF.getSubtarget().enableSubRegLiveness())
+ MRI = &MF.getRegInfo();
+ if (!MRI->subRegLivenessEnabled())
return false;
DEBUG(dbgs() << "Renaming independent subregister live ranges in "
<< MF.getName() << '\n');
LIS = &getAnalysis<LiveIntervals>();
- MRI = &MF.getRegInfo();
TII = MF.getSubtarget().getInstrInfo();
// Iterate over all vregs. Note that we query getNumVirtRegs() the newly
hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: false
-tracksSubRegLiveness: false
liveins:
- { reg: '%x0' }
- { reg: '%w1' }
hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: false
-tracksSubRegLiveness: false
liveins:
- { reg: '%x0' }
- { reg: '%w1' }
hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: false
-tracksSubRegLiveness: false
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
liveins:
- { reg: '%r0' }
- { reg: '%r1' }
hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: false
-tracksSubRegLiveness: false
liveins:
- { reg: '%w0' }
frameInfo:
...
---
-name: float
-tracksSubRegLiveness: true
+name: float
liveins:
- { reg: '%sgpr0_sgpr1' }
frameInfo:
...
---
-name: float
-tracksSubRegLiveness: true
+name: float
liveins:
- { reg: '%sgpr0_sgpr1' }
frameInfo:
...
---
-name: float
-tracksSubRegLiveness: true
+name: float
liveins:
- { reg: '%sgpr0_sgpr1' }
frameInfo:
S_ENDPGM
...
---
-name: float2
-tracksSubRegLiveness: true
+name: float2
liveins:
- { reg: '%sgpr0_sgpr1' }
frameInfo:
hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
liveins:
- { reg: '%r0' }
- { reg: '%r1' }
---
# CHECK: name: foo
# CHECK: tracksRegLiveness: false
-# CHECK-NEXT: tracksSubRegLiveness: false
# CHECK: ...
name: foo
body: |
---
# CHECK: name: bar
# CHECK: tracksRegLiveness: true
-# CHECK-NEXT: tracksSubRegLiveness: true
# CHECK: ...
name: bar
tracksRegLiveness: true
-tracksSubRegLiveness: true
body: |
bb.0:
...
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
hasInlineAsm: true
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
liveins:
- { reg: '%x3' }
- { reg: '%x4' }
hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
exposesReturnsTwice: false
hasInlineAsm: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: g8rc_and_g8rc_nox0 }
- { id: 1, class: g8rc_and_g8rc_nox0 }
hasInlineAsm: false
allVRegsAllocated: false
tracksRegLiveness: true
-tracksSubRegLiveness: false
registers:
- { id: 0, class: g8rc }
- { id: 1, class: g8rc }
alignment: 4
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
liveins:
- { reg: '%rdi' }
- { reg: '%esi' }
alignment: 4
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
liveins:
- { reg: '%rdi' }
- { reg: '%esi' }
alignment: 4
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
liveins:
- { reg: '%rdi' }
- { reg: '%esi' }
alignment: 4
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
liveins:
- { reg: '%rdi' }
- { reg: '%rsi' }
hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
liveins:
- { reg: '%edi' }
- { reg: '%esi' }
hasInlineAsm: false
allVRegsAllocated: true
tracksRegLiveness: true
-tracksSubRegLiveness: false
liveins:
- { reg: '%edi' }
- { reg: '%rsi' }