msp430.h (REG_CLASS_CONTENTS): Add R0 to REG_CLASS_CONTENTS[GEN_REGS].

2018-11-06  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* gcc/config/msp430/msp430.h (REG_CLASS_CONTENTS): Add R0 to
	REG_CLASS_CONTENTS[GEN_REGS].
	(REGNO_REG_CLASS): Return NO_REGS for R2 and R3.

	* gcc/testsuite/gcc.target/msp430/special-regs.c: New test.

From-SVN: r265839

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 644c0f7..d3835d1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-11-06  Jozef Lawrynowicz  <jozef.l@mittosystems.com>
+
+       * gcc/config/msp430/msp430.h (REG_CLASS_CONTENTS): Add R0 to
+       REG_CLASS_CONTENTS[GEN_REGS].
+       (REGNO_REG_CLASS): Return NO_REGS for R2 and R3.
+
 2018-11-06  Jan Hubicka  <jh@suse.cz>
 
         * tree.c (fld_simplified_type_of): Clear TYPELESS_STORAGE flag.

diff --git a/gcc/config/msp430/msp430.h b/gcc/config/msp430/msp430.h
index 6bfe28c..380e63e 100644 (file)
--- a/gcc/config/msp430/msp430.h
+++ b/gcc/config/msp430/msp430.h
@@ -241,10 +241,15 @@ enum reg_class
   0x00000000,             \
   0x00001000,             \
   0x00002000,             \
-  0x0000fff2,             \
+  0x0000fff3,             \
   0x0001ffff              \
 }
 
+/* GENERAL_REGS just means that the "g" and "r" constraints can use these
+   registers.
+   Even though R0 (PC) and R1 (SP) are not "general" in that they can be used
+   for any purpose by the register allocator, they are general in that they can
+   be used by any instruction in any addressing mode.  */
 #define GENERAL_REGS                   GEN_REGS
 #define BASE_REG_CLASS                 GEN_REGS
 #define INDEX_REG_CLASS                        GEN_REGS
@@ -259,7 +264,9 @@ enum reg_class
 
 #define FIRST_PSEUDO_REGISTER          17
 
-#define REGNO_REG_CLASS(REGNO)          ((REGNO) < 17 \
+#define REGNO_REG_CLASS(REGNO)         (REGNO != 2 \
+                                        && REGNO != 3 \
+                                        && REGNO < 17 \
                                         ? GEN_REGS : NO_REGS)
 
 #define TRAMPOLINE_SIZE                        4 /* FIXME */

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6d7683b..1309792 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2018-11-06  Jozef Lawrynowicz  <jozef.l@mittosystems.com>
+
+       * gcc/testsuite/gcc.target/msp430/special-regs.c: New test.
+
 2018-11-06  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
        PR sanitizer/80953

diff --git a/gcc/testsuite/gcc.target/msp430/special-regs.c b/gcc/testsuite/gcc.target/msp430/special-regs.c
new file mode 100644 (file)
index 0000000..c9121e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/msp430/special-regs.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+
+int foo (void)
+{
+  register int pc __asm__("R0");
+  register int sp __asm__("R1");
+  register int cg1 __asm__("R2"); /* { dg-error "the register specified for 'cg1' is not general enough" } */
+  register int cg2 __asm__("R3"); /* { dg-error "the register specified for 'cg2' is not general enough" } */
+
+  asm("" : "=r"(pc));
+  asm("" : "=r"(sp));
+  asm("" : "=r"(cg1));
+  asm("" : "=r"(cg2));
+
+  return pc + sp + cg1 + cg2;
+}