iommu/vt-d: Add a check for 5-level paging support

Add a check to verify IOMMU 5-level paging support. If the CPU supports
supports 5-level paging but the IOMMU does not support it then disable
SVM by not allocating PASID tables.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index e9a56ad..b43dc1e 100644 (file)
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -45,6 +45,10 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
                        !cap_fl1gp_support(iommu->cap))
                return -EINVAL;
 
+       if (cpu_feature_enabled(X86_FEATURE_LA57) &&
+                       !cap_5lp_support(iommu->cap))
+               return -EINVAL;
+
        /* Start at 2 because it's defined as 2^(1+PSS) */
        iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
 

diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index a56bab1..8dad3dd 100644 (file)
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -83,6 +83,7 @@
 /*
  * Decoding Capability Register
  */
+#define cap_5lp_support(c)     (((c) >> 60) & 1)
 #define cap_pi_support(c)      (((c) >> 59) & 1)
 #define cap_fl1gp_support(c)   (((c) >> 56) & 1)
 #define cap_read_drain(c)      (((c) >> 55) & 1)