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[SelectionDAG] Expand VP SDNodes by default.
author
Craig Topper
<craig.topper@sifive.com>
Thu, 6 Apr 2023 01:52:28 +0000
(18:52 -0700)
committer
Craig Topper
<craig.topper@sifive.com>
Thu, 6 Apr 2023 01:52:28 +0000
(18:52 -0700)
Differential Revision: https://reviews.llvm.org/D147643
llvm/lib/CodeGen/TargetLoweringBase.cpp
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diff --git
a/llvm/lib/CodeGen/TargetLoweringBase.cpp
b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index
ac27168
..
6d006ff
100644
(file)
--- a/
llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/
llvm/lib/CodeGen/TargetLoweringBase.cpp
@@
-875,10
+875,10
@@
void TargetLoweringBase::initActions() {
// Named vector shuffles default to expand.
setOperationAction(ISD::VECTOR_SPLICE, VT, Expand);
- // VP
_SREM/UREM
default to expand.
- // TODO: Expand all VP intrinsics.
- setOperationAction(ISD::
VP_SREM
, VT, Expand);
- setOperationAction(ISD::VP_UREM, VT, Expand);
+ // VP
operations
default to expand.
+#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
+ setOperationAction(ISD::
SDOPC
, VT, Expand);
+#include "llvm/IR/VPIntrinsics.def"
}
// Most targets ignore the @llvm.prefetch intrinsic.