[S5PC100] clock 0 div setting

at now, onenand boot is available

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/board/samsung/tickertape/lowlevel_init.S b/board/samsung/tickertape/lowlevel_init.S
index 8e8c6a9..e9635fb 100644 (file)
--- a/board/samsung/tickertape/lowlevel_init.S
+++ b/board/samsung/tickertape/lowlevel_init.S
@@ -189,6 +189,10 @@ system_clock_init:
        ldr r1, =0x1            @ UART ratio set 1 -> 2
        str r1, [r0]
 
+       ldr r0, =S5P_CLK_DIV0
+       ldr r1, =0x11301
+       str r1, [r0]
+
        /* APLL Enable */
        ldr r0, =S5P_APLL_LOCK  
        ldr r1, =0xe10          @ Locktime : 0xe10 = 3600