drm/i915/gvt: filter cmds "srm" and "lrm" in cmd_handler

do not allow "srm" and "lrm" except for GEN8_L3SQCREG4 and 0x21f0.

Cc: Colin Xu <colin.xu@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20201223034508.17031-1-yan.y.zhao@intel.com
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index a598329..7ee1016 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -982,6 +982,17 @@ static int cmd_reg_handler(struct parser_exec_state *s,
                patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
        }
 
+       if (!strncmp(cmd, "srm", 3) ||
+                       !strncmp(cmd, "lrm", 3)) {
+               if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&
+                               offset != 0x21f0) {
+                       gvt_vgpu_err("%s access to register (%x)\n",
+                                       cmd, offset);
+                       return -EPERM;
+               } else
+                       return 0;
+       }
+
        if (is_cmd_update_pdps(offset, s) &&
            cmd_pdp_mmio_update_handler(s, offset, index))
                return -EINVAL;