static int read_sr(struct spi_nor *nor)
{
int ret;
- u8 val;
- ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
+ ret = nor->read_reg(nor, SPINOR_OP_RDSR, nor->bouncebuf, 1);
if (ret < 0) {
pr_err("error %d reading SR\n", (int) ret);
return ret;
}
- return val;
+ return nor->bouncebuf[0];
}
/*
static int read_fsr(struct spi_nor *nor)
{
int ret;
- u8 val;
- ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
+ ret = nor->read_reg(nor, SPINOR_OP_RDFSR, nor->bouncebuf, 1);
if (ret < 0) {
pr_err("error %d reading FSR\n", ret);
return ret;
}
- return val;
+ return nor->bouncebuf[0];
}
/*
static int read_cr(struct spi_nor *nor)
{
int ret;
- u8 val;
- ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
+ ret = nor->read_reg(nor, SPINOR_OP_RDCR, nor->bouncebuf, 1);
if (ret < 0) {
dev_err(nor->dev, "error %d reading CR\n", ret);
return ret;
}
- return val;
+ return nor->bouncebuf[0];
}
/*
*/
static int write_sr(struct spi_nor *nor, u8 val)
{
- nor->cmd_buf[0] = val;
- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
+ nor->bouncebuf[0] = val;
+ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->bouncebuf, 1);
}
/*
* We must clear the register to enable normal behavior.
*/
write_enable(nor);
- nor->cmd_buf[0] = 0;
- nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
+ nor->bouncebuf[0] = 0;
+ nor->write_reg(nor, SPINOR_OP_WREAR,
+ nor->bouncebuf, 1);
write_disable(nor);
}
return status;
default:
/* Spansion style */
- nor->cmd_buf[0] = enable << 7;
- return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
+ nor->bouncebuf[0] = enable << 7;
+ return nor->write_reg(nor, SPINOR_OP_BRWR, nor->bouncebuf, 1);
}
}
static int s3an_sr_ready(struct spi_nor *nor)
{
int ret;
- u8 val;
- ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
+ ret = nor->read_reg(nor, SPINOR_OP_XRDSR, nor->bouncebuf, 1);
if (ret < 0) {
dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
return ret;
}
- return !!(val & XSR_RDY);
+ return !!(nor->bouncebuf[0] & XSR_RDY);
}
static int spi_nor_sr_ready(struct spi_nor *nor)
*/
static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
{
- u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
int i;
if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
* control
*/
for (i = nor->addr_width - 1; i >= 0; i--) {
- buf[i] = addr & 0xff;
+ nor->bouncebuf[i] = addr & 0xff;
addr >>= 8;
}
- return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
+ return nor->write_reg(nor, nor->erase_opcode, nor->bouncebuf,
+ nor->addr_width);
}
/**
*/
static int spansion_quad_enable(struct spi_nor *nor)
{
- u8 sr_cr[2] = {0, CR_QUAD_EN_SPAN};
+ u8 *sr_cr = nor->bouncebuf;
int ret;
+ sr_cr[0] = 0;
+ sr_cr[1] = CR_QUAD_EN_SPAN;
ret = write_sr_cr(nor, sr_cr);
if (ret)
return ret;
*/
static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
{
- u8 sr_cr[2];
+ u8 *sr_cr = nor->bouncebuf;
int ret;
/* Keep the current value of the Status Register. */
static int spansion_read_cr_quad_enable(struct spi_nor *nor)
{
struct device *dev = nor->dev;
- u8 sr_cr[2];
+ u8 *sr_cr = nor->bouncebuf;
int ret;
/* Check current Quad Enable bit value. */
*/
static int sr2_bit7_quad_enable(struct spi_nor *nor)
{
- u8 sr2;
+ u8 *sr2 = nor->bouncebuf;
int ret;
/* Check current Quad Enable bit value. */
- ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
+ ret = nor->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
if (ret)
return ret;
- if (sr2 & SR2_QUAD_EN_BIT7)
+ if (*sr2 & SR2_QUAD_EN_BIT7)
return 0;
/* Update the Quad Enable bit. */
- sr2 |= SR2_QUAD_EN_BIT7;
+ *sr2 |= SR2_QUAD_EN_BIT7;
write_enable(nor);
- ret = nor->write_reg(nor, SPINOR_OP_WRSR2, &sr2, 1);
+ ret = nor->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1);
if (ret < 0) {
dev_err(nor->dev, "error while writing status register 2\n");
return -EINVAL;
}
/* Read back and check it. */
- ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
- if (!(ret > 0 && (sr2 & SR2_QUAD_EN_BIT7))) {
+ ret = nor->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
+ if (!(ret > 0 && (*sr2 & SR2_QUAD_EN_BIT7))) {
dev_err(nor->dev, "SR2 Quad bit not set\n");
return -EINVAL;
}
{
int ret;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- u8 sr_cr[2] = {0};
+ u8 *sr_cr = nor->bouncebuf;
/* Check current Quad Enable bit value. */
ret = read_cr(nor);
static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
{
int tmp;
- u8 id[SPI_NOR_MAX_ID_LEN];
+ u8 *id = nor->bouncebuf;
const struct flash_info *info;
tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
static int s3an_nor_scan(struct spi_nor *nor)
{
int ret;
- u8 val;
- ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
+ ret = nor->read_reg(nor, SPINOR_OP_XRDSR, nor->bouncebuf, 1);
if (ret < 0) {
dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
return ret;
* The current addressing mode can be read from the XRDSR register
* and should not be changed, because is a destructive operation.
*/
- if (val & XSR_PAGESIZE) {
+ if (nor->bouncebuf[0] & XSR_PAGESIZE) {
/* Flash in Power of 2 mode */
nor->page_size = (nor->page_size == 264) ? 256 : 512;
nor->mtd.writebufsize = nor->page_size;
nor->read_proto = SNOR_PROTO_1_1_1;
nor->write_proto = SNOR_PROTO_1_1_1;
+ /*
+ * We need the bounce buffer early to read/write registers when going
+ * through the spi-mem layer (buffers have to be DMA-able).
+ */
+ nor->bouncebuf_size = PAGE_SIZE;
+ nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
+ GFP_KERNEL);
+ if (!nor->bouncebuf)
+ return -ENOMEM;
+
if (name)
info = spi_nor_match_id(name);
/* Try to auto-detect if chip name wasn't specified or not found */