* This is called from smp_prepare_cpus if we've built for SMP, but
* we still need to set it up for PM and firmware ops if not.
*/
- if (!IS_ENABLED(SMP))
+ if (!IS_ENABLED(CONFIG_SMP))
exynos_sysram_init();
--- exynos_cpuidle_init();
+++ if (!of_machine_is_compatible("samsung,exynos5420"))
+++ exynos_cpuidle_init();
+++
exynos_cpufreq_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
+ ++ u32 mpidr = cpu_logical_map(cpu);
+ ++ u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ ++
for (;;) {
- -- /* make cpu1 to be turned off at next WFI command */
- -- if (cpu == 1)
- -- exynos_cpu_power_down(cpu);
+ ++ /* Turn the CPU off on next WFI instruction. */
+ ++ exynos_cpu_power_down(core_id);
- /*
- * here's the WFI
- */
- asm(".word 0xe320f003\n"
- :
- :
- : "memory", "cc");
+ wfi();
- -- if (pen_release == cpu_logical_map(cpu)) {
+ ++ if (pen_release == core_id) {
/*
* OK, proper wakeup, we're done
*/
writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
}
-static void armada_370_xp_cpu_resume(void)
-{
- asm volatile("bl ll_add_cpu_to_smp_group\n\t"
- "bl ll_enable_coherency\n\t"
- "b cpu_resume\n\t");
-}
-
/* No locking is needed because we only access per-CPU registers */
---void armada_370_xp_pmsu_idle_prepare(bool deepidle)
+++int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
{
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
u32 reg;