{
op_true = force_reg (mode, op_true);
- if (!nonimmediate_operand (op_false, mode))
+ if (GET_MODE_SIZE (mode) < 16
+ || !nonimmediate_operand (op_false, mode))
op_false = force_reg (mode, op_false);
emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cmp,
;; XOP parallel XMM conditional moves
(define_insn "*xop_pcmov_<mode>"
- [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
- (if_then_else:MMXMODEI
- (match_operand:MMXMODEI 3 "register_operand" "x")
- (match_operand:MMXMODEI 1 "register_operand" "x")
- (match_operand:MMXMODEI 2 "register_operand" "x")))]
+ [(set (match_operand:MMXMODE124 0 "register_operand" "=x")
+ (if_then_else:MMXMODE124
+ (match_operand:MMXMODE124 3 "register_operand" "x")
+ (match_operand:MMXMODE124 1 "register_operand" "x")
+ (match_operand:MMXMODE124 2 "register_operand" "x")))]
"TARGET_XOP && TARGET_MMX_WITH_SSE"
"vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "sse4arg")])
--- /dev/null
+/* PR target/100581 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mxop" } */
+
+typedef float __attribute__((__vector_size__(8))) v64f32;
+
+v64f32 af, bf, ff_a, ff_b;
+
+v64f32 f() { return ff_a > ff_b ? af : bf; }