[ARM][AArch64] Move common code into ARMTargetParserCommon
authorTomas Matheson <tomas.matheson@arm.com>
Mon, 14 Nov 2022 12:36:23 +0000 (12:36 +0000)
committerTomas Matheson <tomas.matheson@arm.com>
Wed, 16 Nov 2022 18:40:23 +0000 (18:40 +0000)
Differential Revision: https://reviews.llvm.org/D138017

llvm/include/llvm/Support/ARMTargetParser.h
llvm/include/llvm/Support/ARMTargetParserCommon.h
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Support/ARMTargetParserCommon.cpp
llvm/lib/Support/Triple.cpp

index 4254682..8978ed1 100644 (file)
@@ -16,6 +16,7 @@
 
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/ARMTargetParserCommon.h"
 #include <vector>
 
 namespace llvm {
@@ -158,13 +159,6 @@ enum class NeonSupportLevel {
   Crypto    ///< Neon with Crypto
 };
 
-// ISA kinds.
-enum class ISAKind { INVALID = 0, ARM, THUMB, AARCH64 };
-
-// Endianness
-// FIXME: BE8 vs. BE32?
-enum class EndianKind { INVALID = 0, LITTLE, BIG };
-
 // v6/v7/v8 Profile
 enum class ProfileKind { INVALID = 0, A, R, M };
 
@@ -226,7 +220,7 @@ template <typename T> struct ArchNames {
   }
 };
 
-static const ArchNames<ArchKind> ARCHNames[] = {
+static const ArchNames<ArchKind> ARMArchNames[] = {
 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU,            \
                  ARCH_BASE_EXT)                                                \
   {NAME,         sizeof(NAME) - 1,                                             \
@@ -287,8 +281,6 @@ unsigned parseFPU(StringRef FPU);
 ArchKind parseArch(StringRef Arch);
 uint64_t parseArchExt(StringRef ArchExt);
 ArchKind parseCPUArch(StringRef CPU);
-ISAKind parseArchISA(StringRef Arch);
-EndianKind parseArchEndian(StringRef Arch);
 ProfileKind parseArchProfile(StringRef Arch);
 unsigned parseArchVersion(StringRef Arch);
 
index fb296bc..3db8646 100644 (file)
 namespace llvm {
 namespace ARM {
 
+enum class ISAKind { INVALID = 0, ARM, THUMB, AARCH64 };
+
+enum class EndianKind { INVALID = 0, LITTLE, BIG };
+
 /// Converts e.g. "armv8" -> "armv8-a"
 StringRef getArchSynonym(StringRef Arch);
 
@@ -27,6 +31,12 @@ StringRef getArchSynonym(StringRef Arch);
 /// If invalid, return empty string.
 StringRef getCanonicalArchName(StringRef Arch);
 
+// ARM, Thumb, AArch64
+ISAKind parseArchISA(StringRef Arch);
+
+// Little/Big endian
+EndianKind parseArchEndian(StringRef Arch);
+
 } // namespace ARM
 } // namespace llvm
 #endif
index b22fbc3..53db7b5 100644 (file)
@@ -29,7 +29,7 @@ static StringRef getHWDivSynonym(StringRef HWDiv) {
 ARM::ArchKind ARM::parseArch(StringRef Arch) {
   Arch = getCanonicalArchName(Arch);
   StringRef Syn = getArchSynonym(Arch);
-  for (const auto &A : ARCHNames) {
+  for (const auto &A : ARMArchNames) {
     if (A.getName().endswith(Syn))
       return A.ID;
   }
@@ -211,35 +211,6 @@ bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
   return true;
 }
 
-// Little/Big endian
-ARM::EndianKind ARM::parseArchEndian(StringRef Arch) {
-  if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
-      Arch.startswith("aarch64_be"))
-    return EndianKind::BIG;
-
-  if (Arch.startswith("arm") || Arch.startswith("thumb")) {
-    if (Arch.endswith("eb"))
-      return EndianKind::BIG;
-    else
-      return EndianKind::LITTLE;
-  }
-
-  if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32"))
-    return EndianKind::LITTLE;
-
-  return EndianKind::INVALID;
-}
-
-// ARM, Thumb, AArch64
-ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
-  return StringSwitch<ISAKind>(Arch)
-      .StartsWith("aarch64", ISAKind::AARCH64)
-      .StartsWith("arm64", ISAKind::AARCH64)
-      .StartsWith("thumb", ISAKind::THUMB)
-      .StartsWith("arm", ISAKind::ARM)
-      .Default(ISAKind::INVALID);
-}
-
 unsigned ARM::parseFPU(StringRef FPU) {
   StringRef Syn = getFPUSynonym(FPU);
   for (const auto &F : FPUNames) {
@@ -292,7 +263,7 @@ ARM::FPURestriction ARM::getFPURestriction(unsigned FPUKind) {
 
 unsigned ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) {
   if (CPU == "generic")
-    return ARM::ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
+    return ARM::ARMArchNames[static_cast<unsigned>(AK)].DefaultFPU;
 
   return StringSwitch<unsigned>(CPU)
 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)           \
@@ -303,12 +274,12 @@ unsigned ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) {
 
 uint64_t ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) {
   if (CPU == "generic")
-    return ARM::ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
+    return ARM::ARMArchNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
 
   return StringSwitch<uint64_t>(CPU)
 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)           \
   .Case(NAME,                                                                  \
-        ARCHNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions |    \
+        ARMArchNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
             DEFAULT_EXT)
 #include "llvm/Support/ARMTargetParser.def"
   .Default(ARM::AEK_INVALID);
@@ -350,19 +321,19 @@ bool ARM::getExtensionFeatures(uint64_t Extensions,
 }
 
 StringRef ARM::getArchName(ARM::ArchKind AK) {
-  return ARCHNames[static_cast<unsigned>(AK)].getName();
+  return ARMArchNames[static_cast<unsigned>(AK)].getName();
 }
 
 StringRef ARM::getCPUAttr(ARM::ArchKind AK) {
-  return ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
+  return ARMArchNames[static_cast<unsigned>(AK)].getCPUAttr();
 }
 
 StringRef ARM::getSubArch(ARM::ArchKind AK) {
-  return ARCHNames[static_cast<unsigned>(AK)].getSubArch();
+  return ARMArchNames[static_cast<unsigned>(AK)].getSubArch();
 }
 
 unsigned ARM::getArchAttr(ARM::ArchKind AK) {
-  return ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
+  return ARMArchNames[static_cast<unsigned>(AK)].ArchAttr;
 }
 
 StringRef ARM::getArchExtName(uint64_t ArchExtKind) {
index a8fc4f7..1cbf6e1 100644 (file)
@@ -103,3 +103,30 @@ StringRef ARM::getCanonicalArchName(StringRef Arch) {
   // Arch will either be a 'v' name (v7a) or a marketing name (xscale).
   return A;
 }
+
+ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
+  return StringSwitch<ISAKind>(Arch)
+      .StartsWith("aarch64", ISAKind::AARCH64)
+      .StartsWith("arm64", ISAKind::AARCH64)
+      .StartsWith("thumb", ISAKind::THUMB)
+      .StartsWith("arm", ISAKind::ARM)
+      .Default(ISAKind::INVALID);
+}
+
+ARM::EndianKind ARM::parseArchEndian(StringRef Arch) {
+  if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
+      Arch.startswith("aarch64_be"))
+    return EndianKind::BIG;
+
+  if (Arch.startswith("arm") || Arch.startswith("thumb")) {
+    if (Arch.endswith("eb"))
+      return EndianKind::BIG;
+    else
+      return EndianKind::LITTLE;
+  }
+
+  if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32"))
+    return EndianKind::LITTLE;
+
+  return EndianKind::INVALID;
+}
index ab412c1..c0606ec 100644 (file)
@@ -11,6 +11,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/Support/ARMTargetParser.h"
+#include "llvm/Support/ARMTargetParserCommon.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/SwapByteOrder.h"