i386.md (ix86_expand_vector_set): Use vec_merge path for TARGET_MMX_WITH_SSE && TARGE...

	* config/i386/i386.md (ix86_expand_vector_set) <case E_V2SImode>:
	Use vec_merge path for TARGET_MMX_WITH_SSE && TARGET_SSE4_1.
	<case E_V8QImode>: Ditto.
	* config/i386/mmx.md (*mmx_pinsrd): New insn pattern.
	(*mmx_pinsrb): Ditto.

From-SVN: r274328

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 93e600d..082ebe7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-08-13  Uroš Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (ix86_expand_vector_set) <case E_V2SImode>:
+       Use vec_merge path for TARGET_MMX_WITH_SSE && TARGET_SSE4_1.
+       <case E_V8QImode>: Ditto.
+       * config/i386/mmx.md (*mmx_pinsrd): New insn pattern.
+       (*mmx_pinsrb): Ditto.
+
 2019-08-12  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/83250

diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index f6e6d68..718de73 100644 (file)
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -14243,8 +14243,13 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
 
   switch (mode)
     {
-    case E_V2SFmode:
     case E_V2SImode:
+      use_vec_merge = TARGET_MMX_WITH_SSE && TARGET_SSE4_1;
+      if (use_vec_merge)
+       break;
+      /* FALLTHRU */
+
+    case E_V2SFmode:
       if (mmx_ok)
        {
          tmp = gen_reg_rtx (GET_MODE_INNER (mode));
@@ -14409,6 +14414,7 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
       break;
 
     case E_V8QImode:
+      use_vec_merge = TARGET_MMX_WITH_SSE && TARGET_SSE4_1;
       break;
 
     case E_V32QImode:

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 1fffea1..5ae27c8 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1394,6 +1394,36 @@
    (set_attr "type" "mmxcvt,sselog,sselog")
    (set_attr "mode" "DI,TI,TI")])
 
+(define_insn "*mmx_pinsrd"
+  [(set (match_operand:V2SI 0 "register_operand" "=x,Yv")
+        (vec_merge:V2SI
+          (vec_duplicate:V2SI
+            (match_operand:SI 2 "nonimmediate_operand" "rm,rm"))
+         (match_operand:V2SI 1 "register_operand" "0,Yv")
+          (match_operand:SI 3 "const_int_operand")))]
+  "TARGET_MMX_WITH_SSE && TARGET_SSE4_1
+   && ((unsigned) exact_log2 (INTVAL (operands[3]))
+       < GET_MODE_NUNITS (V2SImode))"
+{
+  operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
+  switch (which_alternative)
+    {
+    case 1:
+      return "vpinsrd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+    case 0:
+      return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "prefix_data16" "1")
+   (set_attr "prefix_extra" "1")
+   (set_attr "type" "sselog")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "TI")])
+
 (define_expand "mmx_pinsrw"
   [(set (match_operand:V4HI 0 "register_operand")
         (vec_merge:V4HI
@@ -1444,6 +1474,42 @@
    (set_attr "length_immediate" "1")
    (set_attr "mode" "DI,TI,TI")])
 
+(define_insn "*mmx_pinsrb"
+  [(set (match_operand:V8QI 0 "register_operand" "=x,Yv")
+        (vec_merge:V8QI
+          (vec_duplicate:V8QI
+            (match_operand:QI 2 "nonimmediate_operand" "rm,rm"))
+         (match_operand:V8QI 1 "register_operand" "0,Yv")
+          (match_operand:SI 3 "const_int_operand")))]
+  "TARGET_MMX_WITH_SSE && TARGET_SSE4_1
+   && ((unsigned) exact_log2 (INTVAL (operands[3]))
+       < GET_MODE_NUNITS (V8QImode))"
+{
+  operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
+  switch (which_alternative)
+    {
+    case 1:
+      if (MEM_P (operands[2]))
+       return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+      else
+       return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
+    case 0:
+      if (MEM_P (operands[2]))
+       return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
+      else
+       return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog")
+   (set_attr "prefix_data16" "1")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "TI")])
+
 (define_insn "mmx_pextrw"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
         (zero_extend:SI