!ctx->s->info.fs.early_fragment_tests)
ctx->so->no_earlyz |= ctx->s->info.writes_memory;
+ if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
+ ctx->s->info.fs.post_depth_coverage)
+ so->post_depth_coverage = true;
+
out:
if (ret) {
if (so->ir)
bool per_samp;
+ bool post_depth_coverage;
+
/* Are we using split or merged register file? */
bool mergedregs;
<reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
<!-- enable bits for various FS sysvalue regs: -->
<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
- <bitfield name="UNK1" pos="1" type="boolean"/>
+ <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/>
<bitfield name="FACENESS" pos="2" type="boolean"/>
<bitfield name="SAMPLEID" pos="3" type="boolean"/>
<bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>
.EXT_mutable_descriptor_type = true,
.KHR_pipeline_library = true,
.EXT_graphics_pipeline_library = true,
+ .EXT_post_depth_coverage = true,
};
}
CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_RENDER_CONTROL1_CENTERRHW) |
+ COND(fs->post_depth_coverage, A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE) |
COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
.subgroup_shuffle = true,
.subgroup_arithmetic = true,
.physical_storage_buffer_address = true,
+ .post_depth_coverage = true,
},
};