PCI/ASPM: Use PCI Express Capability accessors

Use PCI Express Capability access functions to simplify PCIe ASPM.

Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 2591603..213753b 100644 (file)
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -125,21 +125,16 @@ static int policy_to_clkpm_state(struct pcie_link_state *link)
 
 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
 {
-       int pos;
-       u16 reg16;
        struct pci_dev *child;
        struct pci_bus *linkbus = link->pdev->subordinate;
 
        list_for_each_entry(child, &linkbus->devices, bus_list) {
-               pos = pci_pcie_cap(child);
-               if (!pos)
-                       return;
-               pci_read_config_word(child, pos + PCI_EXP_LNKCTL, &reg16);
                if (enable)
-                       reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
+                       pcie_capability_set_word(child, PCI_EXP_LNKCTL,
+                                                PCI_EXP_LNKCTL_CLKREQ_EN);
                else
-                       reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
-               pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16);
+                       pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
+                                                  PCI_EXP_LNKCTL_CLKREQ_EN);
        }
        link->clkpm_enabled = !!enable;
 }
@@ -157,7 +152,7 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
 
 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
 {
-       int pos, capable = 1, enabled = 1;
+       int capable = 1, enabled = 1;
        u32 reg32;
        u16 reg16;
        struct pci_dev *child;
@@ -165,16 +160,13 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
 
        /* All functions should have the same cap and state, take the worst */
        list_for_each_entry(child, &linkbus->devices, bus_list) {
-               pos = pci_pcie_cap(child);
-               if (!pos)
-                       return;
-               pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, &reg32);
+               pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);
                if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
                        capable = 0;
                        enabled = 0;
                        break;
                }
-               pci_read_config_word(child, pos + PCI_EXP_LNKCTL, &reg16);
+               pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
                if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
                        enabled = 0;
        }
@@ -190,7 +182,7 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
  */
 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
 {
-       int ppos, cpos, same_clock = 1;
+       int same_clock = 1;
        u16 reg16, parent_reg, child_reg[8];
        unsigned long start_jiffies;
        struct pci_dev *child, *parent = link->pdev;
@@ -203,46 +195,43 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
        BUG_ON(!pci_is_pcie(child));
 
        /* Check downstream component if bit Slot Clock Configuration is 1 */
-       cpos = pci_pcie_cap(child);
-       pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, &reg16);
+       pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);
        if (!(reg16 & PCI_EXP_LNKSTA_SLC))
                same_clock = 0;
 
        /* Check upstream component if bit Slot Clock Configuration is 1 */
-       ppos = pci_pcie_cap(parent);
-       pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, &reg16);
+       pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
        if (!(reg16 & PCI_EXP_LNKSTA_SLC))
                same_clock = 0;
 
        /* Configure downstream component, all functions */
        list_for_each_entry(child, &linkbus->devices, bus_list) {
-               cpos = pci_pcie_cap(child);
-               pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, &reg16);
+               pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
                child_reg[PCI_FUNC(child->devfn)] = reg16;
                if (same_clock)
                        reg16 |= PCI_EXP_LNKCTL_CCC;
                else
                        reg16 &= ~PCI_EXP_LNKCTL_CCC;
-               pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16);
+               pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
        }
 
        /* Configure upstream component */
-       pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, &reg16);
+       pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
        parent_reg = reg16;
        if (same_clock)
                reg16 |= PCI_EXP_LNKCTL_CCC;
        else
                reg16 &= ~PCI_EXP_LNKCTL_CCC;
-       pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
+       pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
 
        /* Retrain link */
        reg16 |= PCI_EXP_LNKCTL_RL;
-       pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
+       pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
 
        /* Wait for link training end. Break out after waiting for timeout */
        start_jiffies = jiffies;
        for (;;) {
-               pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, &reg16);
+               pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
                if (!(reg16 & PCI_EXP_LNKSTA_LT))
                        break;
                if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
@@ -255,12 +244,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
        /* Training failed. Restore common clock configurations */
        dev_printk(KERN_ERR, &parent->dev,
                   "ASPM: Could not configure common clock\n");
-       list_for_each_entry(child, &linkbus->devices, bus_list) {
-               cpos = pci_pcie_cap(child);
-               pci_write_config_word(child, cpos + PCI_EXP_LNKCTL,
-                                     child_reg[PCI_FUNC(child->devfn)]);
-       }
-       pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg);
+       list_for_each_entry(child, &linkbus->devices, bus_list)
+               pcie_capability_write_word(child, PCI_EXP_LNKCTL,
+                                          child_reg[PCI_FUNC(child->devfn)]);
+       pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
 }
 
 /* Convert L0s latency encoding to ns */
@@ -305,16 +292,14 @@ struct aspm_register_info {
 static void pcie_get_aspm_reg(struct pci_dev *pdev,
                              struct aspm_register_info *info)
 {
-       int pos;
        u16 reg16;
        u32 reg32;
 
-       pos = pci_pcie_cap(pdev);
-       pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, &reg32);
+       pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);
        info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
        info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
        info->latency_encoding_l1  = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
-       pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
+       pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);
        info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
 }
 
@@ -420,7 +405,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 
        /* Get and check endpoint acceptable latencies */
        list_for_each_entry(child, &linkbus->devices, bus_list) {
-               int pos;
                u32 reg32, encoding;
                struct aspm_latency *acceptable =
                        &link->acceptable[PCI_FUNC(child->devfn)];
@@ -429,8 +413,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
                    pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
                        continue;
 
-               pos = pci_pcie_cap(child);
-               pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, &reg32);
+               pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
                /* Calculate endpoint L0s acceptable latency */
                encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
                acceptable->l0s = calc_l0s_acceptable(encoding);
@@ -444,13 +427,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 
 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
 {
-       u16 reg16;
-       int pos = pci_pcie_cap(pdev);
-
-       pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
-       reg16 &= ~0x3;
-       reg16 |= val;
-       pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
+       pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val);
 }
 
 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
@@ -505,7 +482,6 @@ static void free_link_state(struct pcie_link_state *link)
 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
 {
        struct pci_dev *child;
-       int pos;
        u32 reg32;
 
        /*
@@ -513,8 +489,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
         * very strange. Disable ASPM for the whole slot
         */
        list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
-               pos = pci_pcie_cap(child);
-               if (!pos)
+               if (!pci_is_pcie(child))
                        return -EINVAL;
 
                /*
@@ -530,7 +505,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
                 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
                 * RBER bit to determine if a function is 1.1 version device
                 */
-               pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, &reg32);
+               pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
                if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
                        dev_printk(KERN_INFO, &child->dev, "disabling ASPM"
                                " on pre-1.1 PCIe device.  You can enable it"