dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator

Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
new file mode 100644 (file)
index 0000000..af77bd8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Video-Output Clock and Reset Generator
+
+maintainers:
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+properties:
+  compatible:
+    const: starfive,jh7110-voutcrg
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Vout Top core
+      - description: Vout Top Ahb
+      - description: Vout Top Axi
+      - description: Vout Top HDMI MCLK
+      - description: I2STX0 BCLK
+      - description: external HDMI pixel
+
+  clock-names:
+    items:
+      - const: vout_src
+      - const: vout_top_ahb
+      - const: vout_top_axi
+      - const: vout_top_hdmitx0_mclk
+      - const: i2stx0_bclk
+      - const: hdmitx0_pixelclk
+
+  resets:
+    maxItems: 1
+    description: Vout Top core
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+  '#reset-cells':
+    const: 1
+    description:
+      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+  power-domains:
+    maxItems: 1
+    description:
+      Vout domain power
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - '#clock-cells'
+  - '#reset-cells'
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+    #include <dt-bindings/power/starfive,jh7110-pmu.h>
+    #include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+    voutcrg: clock-controller@295C0000 {
+        compatible = "starfive,jh7110-voutcrg";
+        reg = <0x295C0000 0x10000>;
+        clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
+                 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
+                 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
+                 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
+                 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
+                 <&hdmitx0_pixelclk>;
+        clock-names = "vout_src", "vout_top_ahb",
+                      "vout_top_axi", "vout_top_hdmitx0_mclk",
+                      "i2stx0_bclk", "hdmitx0_pixelclk";
+        resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+        power-domains = <&pwrc JH7110_PD_VOUT>;
+    };

diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index a329836..0cd963a 100644 (file)
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -270,4 +270,26 @@
 
 #define JH7110_ISPCLK_END                      14
 
+/* VOUTCRG clocks */
+#define JH7110_VOUTCLK_APB                     0
+#define JH7110_VOUTCLK_DC8200_PIX              1
+#define JH7110_VOUTCLK_DSI_SYS                 2
+#define JH7110_VOUTCLK_TX_ESC                  3
+#define JH7110_VOUTCLK_DC8200_AXI              4
+#define JH7110_VOUTCLK_DC8200_CORE             5
+#define JH7110_VOUTCLK_DC8200_AHB              6
+#define JH7110_VOUTCLK_DC8200_PIX0             7
+#define JH7110_VOUTCLK_DC8200_PIX1             8
+#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD                9
+#define JH7110_VOUTCLK_DSITX_APB               10
+#define JH7110_VOUTCLK_DSITX_SYS               11
+#define JH7110_VOUTCLK_DSITX_DPI               12
+#define JH7110_VOUTCLK_DSITX_TXESC             13
+#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC       14
+#define JH7110_VOUTCLK_HDMI_TX_MCLK            15
+#define JH7110_VOUTCLK_HDMI_TX_BCLK            16
+#define JH7110_VOUTCLK_HDMI_TX_SYS             17
+
+#define JH7110_VOUTCLK_END                     18
+
 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */

diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
index 3ed5e0b..57857a4 100644 (file)
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -195,4 +195,20 @@
 
 #define JH7110_ISPRST_END                      12
 
+/* VOUTCRG resets */
+#define JH7110_VOUTRST_DC8200_AXI              0
+#define JH7110_VOUTRST_DC8200_AHB              1
+#define JH7110_VOUTRST_DC8200_CORE             2
+#define JH7110_VOUTRST_DSITX_DPI               3
+#define JH7110_VOUTRST_DSITX_APB               4
+#define JH7110_VOUTRST_DSITX_RXESC             5
+#define JH7110_VOUTRST_DSITX_SYS               6
+#define JH7110_VOUTRST_DSITX_TXBYTEHS          7
+#define JH7110_VOUTRST_DSITX_TXESC             8
+#define JH7110_VOUTRST_HDMI_TX_HDMI            9
+#define JH7110_VOUTRST_MIPITX_DPHY_SYS         10
+#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS    11
+
+#define JH7110_VOUTRST_END                     12
+
 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */