arm64: dts: qcom: sm8350: add IPA information

Add IPA-related nodes and definitions to "sm8350.dtsi", which uses
IPA v4.9.

Signed-off-by: Alex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20210413170553.1778792-2-elder@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index ed0b51b..2fc23f3 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/interconnect/qcom,sm8350.h>
 
 / {
        interrupt-parent = <&intc>;
@@ -391,6 +392,17 @@
                        interrupt-controller;
                        #interrupt-cells = <2>;
                };
+
+               ipa_smp2p_out: ipa-ap-to-modem {
+                       qcom,entry-name = "ipa";
+                       #qcom,smem-state-cells = <1>;
+               };
+
+               ipa_smp2p_in: ipa-modem-to-ap {
+                       qcom,entry-name = "ipa";
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
        };
 
        smp2p-slpi {
@@ -629,6 +641,45 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               ipa: ipa@1e40000 {
+                       compatible = "qcom,sm8350-ipa";
+
+                       iommus = <&apps_smmu 0x5c0 0x0>,
+                                <&apps_smmu 0x5c2 0x0>;
+                       reg = <0 0x1e40000 0 0x8000>,
+                             <0 0x1e50000 0 0x4b20>,
+                             <0 0x1e04000 0 0x23000>;
+                       reg-names = "ipa-reg",
+                                   "ipa-shared",
+                                   "gsi";
+
+                       interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
+                                             <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+                                             <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "ipa",
+                                         "gsi",
+                                         "ipa-clock-query",
+                                         "ipa-setup-ready";
+
+                       clocks = <&rpmhcc RPMH_IPA_CLK>;
+                       clock-names = "core";
+
+                       interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
+                                       <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
+                                       <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
+                       interconnect-names = "ipa_to_llcc",
+                                            "llcc_to_ebi1",
+                                            "appss_to_ipa";
+
+                       qcom,smem-states = <&ipa_smp2p_out 0>,
+                                          <&ipa_smp2p_out 1>;
+                       qcom,smem-state-names = "ipa-clock-enabled-valid",
+                                               "ipa-clock-enabled";
+
+                       status = "disabled";
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex";
                        reg = <0x0 0x01f40000 0x0 0x40000>;