[InstCombine] Regenerate test checks (NFC)

diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-reinterpret.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-reinterpret.ll
index 0748792..868a5d7 100644 (file)
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-reinterpret.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-reinterpret.ll
@@ -1,11 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
 ; RUN: opt -S -passes=instcombine < %s | FileCheck %s
 
 target triple = "aarch64"
 
 define <vscale x 8 x i1> @reinterpret_test_h(<vscale x 8 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_h(
-; CHECK-NOT: convert
-; CHECK: ret <vscale x 8 x i1> %a
+; CHECK-LABEL: define <vscale x 8 x i1> @reinterpret_test_h
+; CHECK-SAME: (<vscale x 8 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    ret <vscale x 8 x i1> [[A]]
+;
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %a)
   %2 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
   ret <vscale x 8 x i1> %2
@@ -14,19 +16,22 @@ define <vscale x 8 x i1> @reinterpret_test_h(<vscale x 8 x i1> %a) {
 ; Reinterprets are not redundant because the second reinterpret zeros the
 ; lanes that don't exist within its input.
 define <vscale x 16 x i1> @reinterpret_test_h_rev(<vscale x 16 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_h_rev(
-; CHECK: %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %a)
-; CHECK-NEXT: %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
-; CHECK-NEXT: ret <vscale x 16 x i1> %2
+; CHECK-LABEL: define <vscale x 16 x i1> @reinterpret_test_h_rev
+; CHECK-SAME: (<vscale x 16 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[A]])
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
+; CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP2]]
+;
   %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %a)
   %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
   ret <vscale x 16 x i1> %2
 }
 
 define <vscale x 4 x i1> @reinterpret_test_w(<vscale x 4 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_w(
-; CHECK-NOT: convert
-; CHECK: ret <vscale x 4 x i1> %a
+; CHECK-LABEL: define <vscale x 4 x i1> @reinterpret_test_w
+; CHECK-SAME: (<vscale x 4 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    ret <vscale x 4 x i1> [[A]]
+;
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %a)
   %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
   ret <vscale x 4 x i1> %2
@@ -35,19 +40,22 @@ define <vscale x 4 x i1> @reinterpret_test_w(<vscale x 4 x i1> %a) {
 ; Reinterprets are not redundant because the second reinterpret zeros the
 ; lanes that don't exist within its input.
 define <vscale x 16 x i1> @reinterpret_test_w_rev(<vscale x 16 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_w_rev(
-; CHECK: %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %a)
-; CHECK-NEXT: %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
-; CHECK-NEXT: ret <vscale x 16 x i1> %2
+; CHECK-LABEL: define <vscale x 16 x i1> @reinterpret_test_w_rev
+; CHECK-SAME: (<vscale x 16 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[A]])
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
+; CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP2]]
+;
   %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %a)
   %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
   ret <vscale x 16 x i1> %2
 }
 
 define <vscale x 2 x i1> @reinterpret_test_d(<vscale x 2 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_d(
-; CHECK-NOT: convert
-; CHECK: ret <vscale x 2 x i1> %a
+; CHECK-LABEL: define <vscale x 2 x i1> @reinterpret_test_d
+; CHECK-SAME: (<vscale x 2 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    ret <vscale x 2 x i1> [[A]]
+;
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %a)
   %2 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
   ret <vscale x 2 x i1> %2
@@ -56,18 +64,22 @@ define <vscale x 2 x i1> @reinterpret_test_d(<vscale x 2 x i1> %a) {
 ; Reinterprets are not redundant because the second reinterpret zeros the
 ; lanes that don't exist within its input.
 define <vscale x 16 x i1> @reinterpret_test_d_rev(<vscale x 16 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_d_rev(
-; CHECK: %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %a)
-; CHECK-NEXT: %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
-; CHECK-NEXT: ret <vscale x 16 x i1> %2
+; CHECK-LABEL: define <vscale x 16 x i1> @reinterpret_test_d_rev
+; CHECK-SAME: (<vscale x 16 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[A]])
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
+; CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP2]]
+;
   %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %a)
   %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
   ret <vscale x 16 x i1> %2
 }
 
 define <vscale x 2 x i1> @reinterpret_test_full_chain(<vscale x 2 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_full_chain(
-; CHECK: ret <vscale x 2 x i1> %a
+; CHECK-LABEL: define <vscale x 2 x i1> @reinterpret_test_full_chain
+; CHECK-SAME: (<vscale x 2 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    ret <vscale x 2 x i1> [[A]]
+;
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %a)
   %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
   %3 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
@@ -80,10 +92,12 @@ define <vscale x 2 x i1> @reinterpret_test_full_chain(<vscale x 2 x i1> %a) {
 ; The last two reinterprets are not necessary, since they are doing the same
 ; work as the first two.
 define <vscale x 4 x i1> @reinterpret_test_partial_chain(<vscale x 2 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_partial_chain(
-; CHECK: %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %a)
-; CHECK-NEXT: %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
-; CHECK-NEXT: ret <vscale x 4 x i1> %2
+; CHECK-LABEL: define <vscale x 4 x i1> @reinterpret_test_partial_chain
+; CHECK-SAME: (<vscale x 2 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[A]])
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[TMP1]])
+; CHECK-NEXT:    ret <vscale x 4 x i1> [[TMP2]]
+;
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %a)
   %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
   %3 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
@@ -94,12 +108,14 @@ define <vscale x 4 x i1> @reinterpret_test_partial_chain(<vscale x 2 x i1> %a) {
 ; The chain cannot be reduced because of the second reinterpret, which causes
 ; zeroing.
 define <vscale x 8 x i1> @reinterpret_test_irreducible_chain(<vscale x 8 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_irreducible_chain(
-; CHECK: %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %a)
-; CHECK-NEXT: %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
-; CHECK-NEXT: %3 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
-; CHECK-NEXT: %4 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %3)
-; CHECK-NEXT: ret <vscale x 8 x i1> %4
+; CHECK-LABEL: define <vscale x 8 x i1> @reinterpret_test_irreducible_chain
+; CHECK-SAME: (<vscale x 8 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[A]])
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP2]])
+; CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[TMP3]])
+; CHECK-NEXT:    ret <vscale x 8 x i1> [[TMP4]]
+;
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %a)
   %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
   %3 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
@@ -110,10 +126,12 @@ define <vscale x 8 x i1> @reinterpret_test_irreducible_chain(<vscale x 8 x i1> %
 ; Here, the candidate list is larger than the number of instructions that we
 ; end up removing.
 define <vscale x 4 x i1> @reinterpret_test_keep_some_candidates(<vscale x 8 x i1> %a) {
-; CHECK-LABEL: @reinterpret_test_keep_some_candidates(
-; CHECK: %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %a)
-; CHECK-NEXT: %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
-; CHECK-NEXT: ret <vscale x 4 x i1> %2
+; CHECK-LABEL: define <vscale x 4 x i1> @reinterpret_test_keep_some_candidates
+; CHECK-SAME: (<vscale x 8 x i1> [[A:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[A]])
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[TMP1]])
+; CHECK-NEXT:    ret <vscale x 4 x i1> [[TMP2]]
+;
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %a)
   %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
   %3 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
@@ -122,17 +140,28 @@ define <vscale x 4 x i1> @reinterpret_test_keep_some_candidates(<vscale x 8 x i1
 }
 
 define <vscale x 2 x i1> @reinterpret_reductions(i32 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %c) {
-; CHECK-LABEL: reinterpret_reductions
-; CHECK-NOT: convert
-; CHECK-NOT: phi <vscale x 16 x i1>
-; CHECK: phi <vscale x 2 x i1> [ %a, %br_phi_a ], [ %b, %br_phi_b ], [ %c, %br_phi_c ]
-; CHECK-NOT: convert
-; CHECK: ret
+; CHECK-LABEL: define <vscale x 2 x i1> @reinterpret_reductions
+; CHECK-SAME: (i32 [[COND:%.*]], <vscale x 2 x i1> [[A:%.*]], <vscale x 2 x i1> [[B:%.*]], <vscale x 2 x i1> [[C:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[COND]], label [[BR_PHI_C:%.*]] [
+; CHECK-NEXT:    i32 43, label [[BR_PHI_A:%.*]]
+; CHECK-NEXT:    i32 45, label [[BR_PHI_B:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       br_phi_a:
+; CHECK-NEXT:    br label [[JOIN:%.*]]
+; CHECK:       br_phi_b:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       br_phi_c:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       join:
+; CHECK-NEXT:    [[PG1:%.*]] = phi <vscale x 2 x i1> [ [[A]], [[BR_PHI_A]] ], [ [[B]], [[BR_PHI_B]] ], [ [[C]], [[BR_PHI_C]] ]
+; CHECK-NEXT:    ret <vscale x 2 x i1> [[PG1]]
+;
 
 entry:
   switch i32 %cond, label %br_phi_c [
-         i32 43, label %br_phi_a
-         i32 45, label %br_phi_b
+  i32 43, label %br_phi_a
+  i32 45, label %br_phi_b
   ]
 
 br_phi_a:
@@ -156,17 +185,32 @@ join:
 ; No transform as the reinterprets are converting from different types (nxv2i1 & nxv4i1)
 ; As the incoming values to the phi must all be the same type, we cannot remove the reinterprets.
 define <vscale x 2 x i1> @reinterpret_reductions_1(i32 %cond, <vscale x 2 x i1> %a, <vscale x 4 x i1> %b, <vscale x 2 x i1> %c) {
-; CHECK-LABEL: reinterpret_reductions_1
-; CHECK: convert
-; CHECK: phi <vscale x 16 x i1> [ %a1, %br_phi_a ], [ %b1, %br_phi_b ], [ %c1, %br_phi_c ]
-; CHECK-NOT: phi <vscale x 2 x i1>
-; CHECK: tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
-; CHECK: ret
+; CHECK-LABEL: define <vscale x 2 x i1> @reinterpret_reductions_1
+; CHECK-SAME: (i32 [[COND:%.*]], <vscale x 2 x i1> [[A:%.*]], <vscale x 4 x i1> [[B:%.*]], <vscale x 2 x i1> [[C:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[COND]], label [[BR_PHI_C:%.*]] [
+; CHECK-NEXT:    i32 43, label [[BR_PHI_A:%.*]]
+; CHECK-NEXT:    i32 45, label [[BR_PHI_B:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       br_phi_a:
+; CHECK-NEXT:    [[A1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[A]])
+; CHECK-NEXT:    br label [[JOIN:%.*]]
+; CHECK:       br_phi_b:
+; CHECK-NEXT:    [[B1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[B]])
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       br_phi_c:
+; CHECK-NEXT:    [[C1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[C]])
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       join:
+; CHECK-NEXT:    [[PG:%.*]] = phi <vscale x 16 x i1> [ [[A1]], [[BR_PHI_A]] ], [ [[B1]], [[BR_PHI_B]] ], [ [[C1]], [[BR_PHI_C]] ]
+; CHECK-NEXT:    [[PG1:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
+; CHECK-NEXT:    ret <vscale x 2 x i1> [[PG1]]
+;
 
 entry:
   switch i32 %cond, label %br_phi_c [
-         i32 43, label %br_phi_a
-         i32 45, label %br_phi_b
+  i32 43, label %br_phi_a
+  i32 45, label %br_phi_b
   ]
 
 br_phi_a:
@@ -190,17 +234,31 @@ join:
 ; No transform. Similar to the the test above, but here only two of the arguments need to
 ; be converted to svbool.
 define <vscale x 2 x i1> @reinterpret_reductions_2(i32 %cond, <vscale x 2 x i1> %a, <vscale x 16 x i1> %b, <vscale x 2 x i1> %c) {
-; CHECK-LABEL: reinterpret_reductions_2
-; CHECK: convert
-; CHECK: phi <vscale x 16 x i1> [ %a1, %br_phi_a ], [ %b, %br_phi_b ], [ %c1, %br_phi_c ]
-; CHECK-NOT: phi <vscale x 2 x i1>
-; CHECK: tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
-; CHECK: ret
+; CHECK-LABEL: define <vscale x 2 x i1> @reinterpret_reductions_2
+; CHECK-SAME: (i32 [[COND:%.*]], <vscale x 2 x i1> [[A:%.*]], <vscale x 16 x i1> [[B:%.*]], <vscale x 2 x i1> [[C:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[COND]], label [[BR_PHI_C:%.*]] [
+; CHECK-NEXT:    i32 43, label [[BR_PHI_A:%.*]]
+; CHECK-NEXT:    i32 45, label [[BR_PHI_B:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       br_phi_a:
+; CHECK-NEXT:    [[A1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[A]])
+; CHECK-NEXT:    br label [[JOIN:%.*]]
+; CHECK:       br_phi_b:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       br_phi_c:
+; CHECK-NEXT:    [[C1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[C]])
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       join:
+; CHECK-NEXT:    [[PG:%.*]] = phi <vscale x 16 x i1> [ [[A1]], [[BR_PHI_A]] ], [ [[B]], [[BR_PHI_B]] ], [ [[C1]], [[BR_PHI_C]] ]
+; CHECK-NEXT:    [[PG1:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
+; CHECK-NEXT:    ret <vscale x 2 x i1> [[PG1]]
+;
 
 entry:
   switch i32 %cond, label %br_phi_c [
-         i32 43, label %br_phi_a
-         i32 45, label %br_phi_b
+  i32 43, label %br_phi_a
+  i32 45, label %br_phi_b
   ]
 
 br_phi_a:
@@ -223,15 +281,31 @@ join:
 ; Similar to reinterpret_reductions but the reinterprets remain because the
 ; original phi cannot be removed (i.e. prefer reinterprets over multiple phis).
 define <vscale x 16 x i1> @reinterpret_reductions3(i32 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %c) {
-; CHECK-LABEL: reinterpret_reductions3
-; CHECK: phi <vscale x 16 x i1> [ %a1, %br_phi_a ], [ %b1, %br_phi_b ], [ %c1, %br_phi_c ]
-; CHECK-NOT: phi <vscale x 2 x i1>
-; CHECK: ret <vscale x 16 x i1> %pg
+; CHECK-LABEL: define <vscale x 16 x i1> @reinterpret_reductions3
+; CHECK-SAME: (i32 [[COND:%.*]], <vscale x 2 x i1> [[A:%.*]], <vscale x 2 x i1> [[B:%.*]], <vscale x 2 x i1> [[C:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[COND]], label [[BR_PHI_C:%.*]] [
+; CHECK-NEXT:    i32 43, label [[BR_PHI_A:%.*]]
+; CHECK-NEXT:    i32 45, label [[BR_PHI_B:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       br_phi_a:
+; CHECK-NEXT:    [[A1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[A]])
+; CHECK-NEXT:    br label [[JOIN:%.*]]
+; CHECK:       br_phi_b:
+; CHECK-NEXT:    [[B1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[B]])
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       br_phi_c:
+; CHECK-NEXT:    [[C1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[C]])
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       join:
+; CHECK-NEXT:    [[PG:%.*]] = phi <vscale x 16 x i1> [ [[A1]], [[BR_PHI_A]] ], [ [[B1]], [[BR_PHI_B]] ], [ [[C1]], [[BR_PHI_C]] ]
+; CHECK-NEXT:    ret <vscale x 16 x i1> [[PG]]
+;
 
 entry:
   switch i32 %cond, label %br_phi_c [
-         i32 43, label %br_phi_a
-         i32 45, label %br_phi_b
+  i32 43, label %br_phi_a
+  i32 45, label %br_phi_b
   ]
 
 br_phi_a: