+++ /dev/null
-# sft-riscvpi-linux-5.10
-
# SPDX-License-Identifier: GPL-2.0
-subdir-y += evb-overlay
+subdir-y += evb-overlay vf2-overlay
dtb-$(CONFIG_SOC_STARFIVE_JH7110) += jh7110-visionfive-v2.dtb \
jh7110-evb.dtb \
jh7110-fpga.dtb \
jh7110-evb-uart1-rgb2hdmi.dtb \
jh7110-evb-uart4-emmc-spdif.dtb \
jh7110-evb-uart5-pwm-i2c-tdm.dtb\
- jh7110-evb-usbdevice.dtb
+ jh7110-evb-usbdevice.dtb \
+ jh7110-visionfive-v2-A10.dtb \
+ jh7110-visionfive-v2-A11.dtb \
+ jh7110-visionfive-v2-wm8960.dtb \
+ jh7110-visionfive-v2-ac108.dtb
reg = <0x10>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
- //reset-gpio = <&gpio 10 0>;
+ //reset-gpio = <&gpio 18 0>;
//DOVDD-supply = <&v2v8>;
- pinctrl-names = "default", "power_up", "power_down";
- pinctrl-0 = <&csi_pins_default>;
- pinctrl-1 = <&csi_pins_pwup>;
- pinctrl-2 = <&csi_pins_pwdn>;
rotation = <0>;
orientation = <1>; //CAMERA_ORIENTATION_BACK
&mipi_dsi {
status = "okay";
+
+ port {
+ dsi_out_port: endpoint@0 {
+ remote-endpoint = <&panel_dsi_port>;
+ };
+ dsi_in_port: endpoint@1 {
+ remote-endpoint = <&mipi_out>;
+ };
+ };
+
+ mipi_panel: panel@0 {
+ /*compatible = "";*/
+ status = "okay";
+ };
};
&mipi_dphy {
};
};
- csi_pins_default: csi-pins-default {
- csi-pins-default {
- starfive,pins = <PAD_GPIO10>;
- starfive,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
- starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
- starfive,pin-gpio-dout = <GPO_LOW>;
- starfive,pin-gpio-doen = <OEN_LOW>;
- };
- };
-
- csi_pins_pwup: csi-pins-pwup {
- csi-pins-pwup {
- starfive,pins = <PAD_GPIO10>;
- starfive,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
- starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
- starfive,pin-gpio-dout = <GPO_HIGH>;
- starfive,pin-gpio-doen = <OEN_LOW>;
- };
- };
-
- csi_pins_pwdn: csi-pins-pwdn {
- csi-pins-pwdn {
- starfive,pins = <PAD_GPIO10>;
- starfive,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
- starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
- starfive,pin-gpio-dout = <GPO_LOW>;
- starfive,pin-gpio-doen = <OEN_LOW>;
- };
- };
-
mmc0_pins: mmc0-pins {
mmc0-pins-rest {
starfive,pins = <PAD_GPIO22>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ * For VisionFive2 version A1.0
+ */
+
+/dts-v1/;
+#include "jh7110-visionfive-v2.dtsi"
+
+/ {
+ model = "StarFive VisionFive V2";
+ compatible = "starfive,visionfive-v2", "starfive,jh7110";
+};
+
+&gpio {
+ uart0_pins: uart0-pins {
+ uart0-pins-tx {
+ starfive,pins = <PAD_GPIO41>;
+ starfive,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ uart0-pins-rx {
+ starfive,pins = <PAD_GPIO40>;
+ starfive,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_UART0_SIN>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ i2c2-pins-scl {
+ starfive,pins = <PAD_GPIO11>;
+ starfive,pinmux = <PAD_GPIO11_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C2_IC_CLK_OE>;
+ starfive,pin-gpio-din = <GPI_I2C2_IC_CLK_IN_A>;
+ };
+
+ i2c2-pins-sda {
+ starfive,pins = <PAD_GPIO9>;
+ starfive,pinmux = <PAD_GPIO9_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C2_IC_DATA_OE>;
+ starfive,pin-gpio-din = <GPI_I2C2_IC_DATA_IN_A>;
+ };
+ };
+
+ mmc0_pins: mmc0-pins {
+ mmc0-pins-rest {
+ starfive,pins = <PAD_GPIO22>;
+ starfive,pinmux = <PAD_GPIO22_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_SDIO0_RST_N>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ sdcard1_pins: sdcard1-pins {
+ sdcard1-pins0 {
+ starfive,pins = <PAD_GPIO4>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sdcard1-pins1 {
+ starfive,pins = <PAD_GPIO5>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CCMD_IN>;
+ };
+
+ sdcard1-pins2 {
+ starfive,pins = <PAD_GPIO0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_0>;
+ };
+
+ sdcard1-pins3 {
+ starfive,pins = <PAD_GPIO1>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_1>;
+ };
+
+ sdcard1-pins4 {
+ starfive,pins = <PAD_GPIO2>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_2>;
+ };
+
+ sdcard1-pins5 {
+ starfive,pins = <PAD_GPIO3>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_3>;
+ };
+ };
+
+ inno_hdmi_pins: inno_hdmi-pins {
+ inno_hdmi-scl {
+ starfive,pins = <PAD_GPIO7>;
+ //starfive,pinmux = <PAD_GPIO7_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SCL_OUT>;
+ starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SCL_OEN>;
+ starfive,pin-gpio-din = <GPI_HDMI0_DDC_SCL_IN>;
+ };
+
+ inno_hdmi-sda {
+ starfive,pins = <PAD_GPIO8>;
+ //starfive,pinmux = <PAD_GPIO8_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SDA_OUT>;
+ starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SDA_OEN>;
+ starfive,pin-gpio-din = <GPI_HDMI0_DDC_SDA_IN>;
+ };
+ inno_hdmi-cec-pins {
+ starfive,pins = <PAD_GPIO14>;
+ //starfive,pinmux = <PAD_GPIO14_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-doen = <OEN_HDMI0_CEC_SDA_OEN>;
+ starfive,pin-gpio-dout = <GPO_HDMI0_CEC_SDA_OUT>;
+ starfive,pin-gpio-din = <GPI_HDMI0_CEC_SDA_IN>;
+ };
+ inno_hdmi-hpd-pins {
+ starfive,pins = <PAD_GPIO15>;
+ //starfive,pinmux = <PAD_GPIO15_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_HDMI0_HPD>;
+ };
+ };
+
+ pcie0_vbus_default: pcie0_vbus_default {
+ drive-vbus-pin {
+ starfive,pins = <PAD_GPIO25>;
+ starfive,pinmux = <PAD_GPIO25_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_HIGH>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&sdio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "okay";
+};
+
+&sdio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard1_pins>;
+ //cd-gpios = <&gpio 6 0>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&inno_hdmi_pins>;
+};
+
+&pcie0 {
+ pinctrl-names = "default", "perst-default", "perst-active";
+ pinctrl-0 = <&pcie0_wake_default>,
+ <&pcie0_clkreq_default>,
+ <&pcie0_vbus_default>;
+ pinctrl-1 = <&pcie0_perst_default>;
+ pinctrl-2 = <&pcie0_perst_active>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ * For VisionFive2 version A1.1
+ */
+
+/dts-v1/;
+#include "jh7110-visionfive-v2.dtsi"
+
+/ {
+ model = "StarFive VisionFive V2";
+ compatible = "starfive,visionfive-v2", "starfive,jh7110";
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
+
+};
+
+&gpio {
+ uart0_pins: uart0-pins {
+ uart0-pins-tx {
+ starfive,pins = <PAD_GPIO5>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ uart0-pins-rx {
+ starfive,pins = <PAD_GPIO6>;
+ starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_UART0_SIN>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ i2c2-pins-scl {
+ starfive,pins = <PAD_GPIO3>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C2_IC_CLK_OE>;
+ starfive,pin-gpio-din = <GPI_I2C2_IC_CLK_IN_A>;
+ };
+
+ i2c2-pins-sda {
+ starfive,pins = <PAD_GPIO2>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C2_IC_DATA_OE>;
+ starfive,pin-gpio-din = <GPI_I2C2_IC_DATA_IN_A>;
+ };
+ };
+
+ mmc0_pins: mmc0-pins {
+ mmc0-pins-rest {
+ starfive,pins = <PAD_GPIO62>;
+ starfive,pinmux = <PAD_GPIO62_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_SDIO0_RST_N>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ sdcard1_pins: sdcard1-pins {
+ sdcard1-pins0 {
+ starfive,pins = <PAD_GPIO10>;
+ starfive,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sdcard1-pins1 {
+ starfive,pins = <PAD_GPIO9>;
+ starfive,pinmux = <PAD_GPIO9_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CCMD_IN>;
+ };
+
+ sdcard1-pins2 {
+ starfive,pins = <PAD_GPIO11>;
+ starfive,pinmux = <PAD_GPIO11_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_0>;
+ };
+
+ sdcard1-pins3 {
+ starfive,pins = <PAD_GPIO12>;
+ starfive,pinmux = <PAD_GPIO12_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_1>;
+ };
+
+ sdcard1-pins4 {
+ starfive,pins = <PAD_GPIO7>;
+ starfive,pinmux = <PAD_GPIO7_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_2>;
+ };
+
+ sdcard1-pins5 {
+ starfive,pins = <PAD_GPIO8>;
+ starfive,pinmux = <PAD_GPIO8_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_3>;
+ };
+ };
+
+ inno_hdmi_pins: inno_hdmi-pins {
+ inno_hdmi-scl {
+ starfive,pins = <PAD_GPIO0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SCL_OUT>;
+ starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SCL_OEN>;
+ starfive,pin-gpio-din = <GPI_HDMI0_DDC_SCL_IN>;
+ };
+
+ inno_hdmi-sda {
+ starfive,pins = <PAD_GPIO1>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SDA_OUT>;
+ starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SDA_OEN>;
+ starfive,pin-gpio-din = <GPI_HDMI0_DDC_SDA_IN>;
+ };
+ inno_hdmi-cec-pins {
+ starfive,pins = <PAD_GPIO14>;
+ //starfive,pinmux = <PAD_GPIO14_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-doen = <OEN_HDMI0_CEC_SDA_OEN>;
+ starfive,pin-gpio-dout = <GPO_HDMI0_CEC_SDA_OUT>;
+ starfive,pin-gpio-din = <GPI_HDMI0_CEC_SDA_IN>;
+ };
+ inno_hdmi-hpd-pins {
+ starfive,pins = <PAD_GPIO15>;
+ //starfive,pinmux = <PAD_GPIO15_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_HDMI0_HPD>;
+ };
+ };
+
+ pcie0_vbus_default: pcie0_vbus_default {
+ drive-vbus-pin {
+ starfive,pins = <PAD_GPIO25>;
+ starfive,pinmux = <PAD_GPIO25_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_HIGH>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&sdio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "okay";
+};
+
+&sdio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard1_pins>;
+ //cd-gpios = <&gpio 41 0>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&inno_hdmi_pins>;
+};
+
+&pcie0 {
+ pinctrl-names = "default", "perst-default", "perst-active";
+ pinctrl-0 = <&pcie0_wake_default>,
+ <&pcie0_clkreq_default>,
+ <&pcie0_vbus_default>;
+ pinctrl-1 = <&pcie0_perst_default>;
+ pinctrl-2 = <&pcie0_perst_active>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-visionfive-v2.dts"
+#include "codecs/sf_ac108.dtsi"
+
+&i2c0 {
+ ac108_a: ac108@3b {
+ compatible = "x-power,ac108_0";
+ reg = <0x3b>;
+ #sound-dai-cells = <0>;
+ data-protocol = <0>;
+ };
+};
+
+&i2srx_3ch {
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-visionfive-v2.dts"
+#include "codecs/sf_wm8960.dtsi"
+
+&i2c0 {
+ wm8960: codec@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+
+ wlf,shared-lrclk;
+ };
+};
+
+&i2srx_3ch {
+ status = "okay";
+};
+
+&i2stx_4ch1 {
+ status = "okay";
+};
*/
/dts-v1/;
-#include "jh7110-common.dtsi"
+#include "jh7110-visionfive-v2.dtsi"
+#include "codecs/sf_hdmi.dtsi"
/ {
model = "StarFive VisionFive V2";
compatible = "starfive,visionfive-v2", "starfive,jh7110";
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
+
+};
+
+&gpio {
+ uart0_pins: uart0-pins {
+ uart0-pins-tx {
+ starfive,pins = <PAD_GPIO5>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ uart0-pins-rx {
+ starfive,pins = <PAD_GPIO6>;
+ starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_UART0_SIN>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ i2c2-pins-scl {
+ starfive,pins = <PAD_GPIO3>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C2_IC_CLK_OE>;
+ starfive,pin-gpio-din = <GPI_I2C2_IC_CLK_IN_A>;
+ };
+
+ i2c2-pins-sda {
+ starfive,pins = <PAD_GPIO2>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C2_IC_DATA_OE>;
+ starfive,pin-gpio-din = <GPI_I2C2_IC_DATA_IN_A>;
+ };
+ };
+
+ mmc0_pins: mmc0-pins {
+ mmc0-pins-rest {
+ starfive,pins = <PAD_GPIO62>;
+ starfive,pinmux = <PAD_GPIO62_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_SDIO0_RST_N>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ sdcard1_pins: sdcard1-pins {
+ sdcard1-pins0 {
+ starfive,pins = <PAD_GPIO10>;
+ starfive,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sdcard1-pins1 {
+ starfive,pins = <PAD_GPIO9>;
+ starfive,pinmux = <PAD_GPIO9_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CCMD_IN>;
+ };
+
+ sdcard1-pins2 {
+ starfive,pins = <PAD_GPIO11>;
+ starfive,pinmux = <PAD_GPIO11_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_0>;
+ };
+
+ sdcard1-pins3 {
+ starfive,pins = <PAD_GPIO12>;
+ starfive,pinmux = <PAD_GPIO12_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_1>;
+ };
+
+ sdcard1-pins4 {
+ starfive,pins = <PAD_GPIO7>;
+ starfive,pinmux = <PAD_GPIO7_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_2>;
+ };
+
+ sdcard1-pins5 {
+ starfive,pins = <PAD_GPIO8>;
+ starfive,pinmux = <PAD_GPIO8_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;
+ starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;
+ starfive,pin-gpio-din = <GPI_SDIO1_CDATA_IN_3>;
+ };
+ };
+
+ inno_hdmi_pins: inno_hdmi-pins {
+ inno_hdmi-scl {
+ starfive,pins = <PAD_GPIO0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SCL_OUT>;
+ starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SCL_OEN>;
+ starfive,pin-gpio-din = <GPI_HDMI0_DDC_SCL_IN>;
+ };
+
+ inno_hdmi-sda {
+ starfive,pins = <PAD_GPIO1>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SDA_OUT>;
+ starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SDA_OEN>;
+ starfive,pin-gpio-din = <GPI_HDMI0_DDC_SDA_IN>;
+ };
+ inno_hdmi-cec-pins {
+ starfive,pins = <PAD_GPIO14>;
+ //starfive,pinmux = <PAD_GPIO14_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-doen = <OEN_HDMI0_CEC_SDA_OEN>;
+ starfive,pin-gpio-dout = <GPO_HDMI0_CEC_SDA_OUT>;
+ starfive,pin-gpio-din = <GPI_HDMI0_CEC_SDA_IN>;
+ };
+ inno_hdmi-hpd-pins {
+ starfive,pins = <PAD_GPIO15>;
+ //starfive,pinmux = <PAD_GPIO15_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_HDMI0_HPD>;
+ };
+ };
+
+ mclk_ext_pins: mclk_ext_pins {
+ mclk_ext_pins {
+ starfive,pins = <PAD_GPIO4>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-din = <GPI_CRG0_EXT_MCLK>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
};
-&timer {
- clock-frequency = <24000000>;
-};
\ No newline at end of file
+&sdio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "okay";
+};
+
+&sdio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard1_pins>;
+ //cd-gpios = <&gpio 41 0>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&inno_hdmi_pins>;
+};
+
+&i2stx_4ch0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mclk_ext_pins>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
+#include "jh7110.dtsi"
+#include "codecs/sf_pwmdac.dtsi"
+
+/ {
+ model = "StarFive VisionFive V2";
+ compatible = "starfive,visionfive-v2", "starfive,jh7110";
+
+ aliases {
+ spi0 = &qspi;
+ gpio0 = &gpio;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdio0;
+ mmc1 = &sdio1;
+ serial0 = &uart0;
+ serial3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+
+ chosen {
+ linux,initrd-start = <0x0 0x46100000>;
+ linux,initrd-end = <0x0 0x4c000000>;
+ stdout-path = "serial0:115200";
+ #bootargs = "debug console=ttyS0 rootwait";
+ };
+
+ cpus {
+ timebase-frequency = <4000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x20000000>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
+ linux,cma-default;
+ };
+
+ e24_mem: e24@c0000000 {
+ no-map;
+ reg = <0x0 0xc0110000 0x0 0xf0000>;
+ };
+
+ xrp_reserved: xrpbuffer@f0000000 {
+ reg = <0x0 0xf0000000 0x0 0x01ffffff
+ 0x0 0xf2000000 0x0 0x00001000
+ 0x0 0xf2001000 0x0 0x00fff000
+ 0x0 0xf3000000 0x0 0x00001000>;
+ };
+
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-ack {
+ gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ label = "ack";
+ };
+ };
+};
+
+&gpio {
+ i2c0_pins: i2c0-pins {
+ i2c0-pins-scl {
+ starfive,pins = <PAD_GPIO57>;
+ starfive,pinmux = <PAD_GPIO57_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C0_IC_CLK_OE>;
+ starfive,pin-gpio-din = <GPI_I2C0_IC_CLK_IN_A>;
+ };
+
+ i2c0-pins-sda {
+ starfive,pins = <PAD_GPIO58>;
+ starfive,pinmux = <PAD_GPIO58_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C0_IC_DATA_OE>;
+ starfive,pin-gpio-din = <GPI_I2C0_IC_DATA_IN_A>;
+ };
+ };
+
+ i2c5_pins: i2c5-pins {
+ i2c5-pins-scl {
+ starfive,pins = <PAD_GPIO19>;
+ starfive,pinmux = <PAD_GPIO19_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C5_IC_CLK_OE>;
+ starfive,pin-gpio-din = <GPI_I2C5_IC_CLK_IN_A>;
+ };
+
+ i2c5-pins-sda {
+ starfive,pins = <PAD_GPIO20>;
+ starfive,pinmux = <PAD_GPIO20_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C5_IC_DATA_OE>;
+ starfive,pin-gpio-din = <GPI_I2C5_IC_DATA_IN_A>;
+ };
+ };
+
+ i2c6_pins: i2c6-pins {
+ i2c6-pins-scl {
+ starfive,pins = <PAD_GPIO16>;
+ starfive,pinmux = <PAD_GPIO16_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C6_IC_CLK_OE>;
+ starfive,pin-gpio-din = <GPI_I2C6_IC_CLK_IN_A>;
+ };
+
+ i2c6-pins-sda {
+ starfive,pins = <PAD_GPIO17>;
+ starfive,pinmux = <PAD_GPIO17_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C6_IC_DATA_OE>;
+ starfive,pin-gpio-din = <GPI_I2C6_IC_DATA_IN_A>;
+ };
+ };
+
+ csi_pins: csi-pins {
+ csi-pins-pwdn {
+ starfive,pins = <PAD_GPIO18>;
+ starfive,pinmux = <PAD_GPIO18_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_HIGH>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ pwmdac0_pins: pwmdac0-pins {
+ pwmdac0-pins-left {
+ starfive,pins = <PAD_GPIO33>;
+ starfive,pinmux = <PAD_GPIO33_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_PWMDAC0_LEFT_OUTPUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ pwmdac0-pins-right {
+ starfive,pins = <PAD_GPIO34>;
+ starfive,pinmux = <PAD_GPIO34_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_PWMDAC0_RIGHT_OUTPUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ pwm_ch0-pins {
+ starfive,pins = <PAD_GPIO46>;
+ starfive,pinmux = <PAD_GPIO46_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_PTC0_PWM_0>;
+ starfive,pin-gpio-doen = <OEN_PTC0_PWM_0_OE_N>;
+ };
+
+ pwm_ch1-pins {
+ starfive,pins = <PAD_GPIO59>;
+ starfive,pinmux = <PAD_GPIO59_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_PTC0_PWM_1>;
+ starfive,pin-gpio-doen = <OEN_PTC0_PWM_1_OE_N>;
+ };
+ };
+
+ ssp0_pins: ssp0-pins {
+ ssp0-pins_tx {
+ starfive,pins = <PAD_GPIO52>;
+ starfive,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_SPI0_SSPTXD>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ ssp0-pins_rx {
+ starfive,pins = <PAD_GPIO53>;
+ starfive,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_SPI0_SSPRXD>;
+ };
+
+ ssp0-pins_clk {
+ starfive,pins = <PAD_GPIO48>;
+ starfive,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_SPI0_SSPCLKOUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ ssp0-pins_cs {
+ starfive,pins = <PAD_GPIO49>;
+ starfive,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_SPI0_SSPFSSOUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ pcie0_perst_default: pcie0_perst_default {
+ perst-pins {
+ starfive,pins = <PAD_GPIO26>;
+ starfive,pinmux = <PAD_GPIO26_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_HIGH>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ pcie0_perst_active: pcie0_perst_active {
+ perst-pins {
+ starfive,pins = <PAD_GPIO26>;
+ starfive,pinmux = <PAD_GPIO26_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ pcie0_wake_default: pcie0_wake_default {
+ wake-pins {
+ starfive,pins = <PAD_GPIO32>;
+ starfive,pinmux = <PAD_GPIO32_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ };
+ };
+
+ pcie0_clkreq_default: pcie0_clkreq_default {
+ clkreq-pins {
+ starfive,pins = <PAD_GPIO27>;
+ starfive,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ };
+ };
+
+ pcie1_perst_default: pcie1_perst_default {
+ perst-pins {
+ starfive,pins = <PAD_GPIO28>;
+ starfive,pinmux = <PAD_GPIO28_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_HIGH>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ pcie1_perst_active: pcie1_perst_active {
+ perst-pins {
+ starfive,pins = <PAD_GPIO28>;
+ starfive,pinmux = <PAD_GPIO28_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ pcie1_wake_default: pcie1_wake_default {
+ wake-pins {
+ starfive,pins = <PAD_GPIO21>;
+ starfive,pinmux = <PAD_GPIO21_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ };
+ };
+
+ pcie1_clkreq_default: pcie1_clkreq_default {
+ clkreq-pins {
+ starfive,pins = <PAD_GPIO29>;
+ starfive,pinmux = <PAD_GPIO29_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ };
+ };
+
+ usb_pins: usb-pins {
+ drive-vbus-pin {
+ starfive,pins = <PAD_GPIO25>;
+ starfive,pinmux = <PAD_GPIO25_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_USB0_DRIVE_VBUS_IO>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ i2srx_pins: i2srx-pins {
+ i2srx-pins0 {
+ starfive,pins = <PAD_GPIO61>;
+ starfive,pinmux = <PAD_GPIO61_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_I2SRX0_EXT_SDIN0>;
+ };
+ };
+
+ i2s_clk_pins: i2s-clk0 {
+ i2s-clk0_bclk {
+ starfive,pins = <PAD_GPIO38>;
+ starfive,pinmux = <PAD_GPIO38_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-din = <GPI_I2STX0_BCLK_SLV GPI_I2SRX0_BCLK_SLV>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ };
+
+ i2s-clk0_lrclk {
+ starfive,pins = <PAD_GPIO63>;
+ starfive,pinmux = <PAD_GPIO63_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-din = <GPI_I2STX0_LRCK_SLV GPI_I2SRX0_LRCK_SLV>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ };
+ };
+
+ i2stx_pins: i2stx-pins {
+ i2stx-pins0 {
+ starfive,pins = <PAD_GPIO44>;
+ starfive,pinmux = <PAD_GPIO44_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+ starfive,pin-gpio-dout = <GPO_I2STX_4CH1_SDO0>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&dma {
+ status = "okay";
+};
+
+&trng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&sec_dma {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ auto_calc_scl_lhcnt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ auto_calc_scl_lhcnt;
+ status = "okay";
+
+ seeed_plane_i2c@45 {
+ compatible = "seeed_panel";
+ reg = <0x45>;
+
+ port {
+ panel_out0: endpoint {
+ remote-endpoint = <&dsi0_output>;
+ };
+ };
+ };
+
+ panel_radxa@19 {
+ compatible ="starfive_jadard";
+ reg = <0x19>;
+ reset-gpio = <&gpio 23 0>;
+ enable-gpio = <&gpio 22 0>;
+
+ port {
+ panel_out1: endpoint {
+ remote-endpoint = <&dsi1_output>;
+ };
+ };
+ };
+
+};
+
+&i2c5 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ auto_calc_scl_lhcnt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ pmic: axp15060_reg@36 {
+ compatible = "stf,axp15060-regulator";
+ reg = <0x36>;
+
+ regulators {
+ mipi_0p9: ALDO1 {
+ regulator-boot-on;
+ regulator-compatible = "mipi_0p9";
+ regulator-name = "mipi_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ };
+ hdmi_0p9: ALDO5 {
+ regulator-boot-on;
+ regulator-compatible = "hdmi_0p9";
+ regulator-name = "hdmi_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ };
+ hdmi_1p8: ALDO3 {
+ regulator-boot-on;
+ regulator-compatible = "hdmi_1p8";
+ regulator-name = "hdmi_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ cpu_vdd: DCDC2 {
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-compatible = "cpu_vdd";
+ regulator-name = "cpu_vdd";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1540000>;
+ };
+ };
+ };
+};
+
+&i2c6 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ auto_calc_scl_lhcnt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ status = "okay";
+
+ imx219: imx219@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ //reset-gpio = <&gpio 18 0>;
+ //DOVDD-supply = <&v2v8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi_pins>;
+ rotation = <0>;
+ orientation = <1>; //CAMERA_ORIENTATION_BACK
+
+ port {
+ /* CSI2 bus endpoint */
+ imx219_to_csi2rx0: endpoint {
+ remote-endpoint = <&csi2rx0_from_imx219>;
+ bus-type = <4>; /* MIPI CSI-2 D-PHY */
+ clock-lanes = <4>;
+ data-lanes = <0 1>;
+ lane-polarities = <0 0 0>;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+};
+
+&sdio0 {
+ max-frequency = <100000000>;
+ card-detect-delay = <300>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ cap-mmc-hw-reset;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
+&sdio1 {
+ max-frequency = <100000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
+&vin_sysctl {
+ /* when use dvp open this pinctrl*/
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* CSI2 bus endpoint */
+ csi2rx0_from_imx219: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&imx219_to_csi2rx0>;
+ bus-type = <4>; /* MIPI CSI-2 D-PHY */
+ clock-lanes = <4>;
+ data-lanes = <0 1>;
+ lane-polarities = <0 0 0>;
+ status = "okay";
+ };
+ };
+ };
+};
+
+&sfctemp {
+ status = "okay";
+};
+
+&jpu {
+ status = "okay";
+};
+
+&vpu_dec {
+ status = "okay";
+};
+
+&vpu_enc {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ rxc_dly_en = <1>;
+ tx_delay_sel_fe = <5>;
+ tx_delay_sel = <0xa>;
+ tx_inverted_10 = <0x1>;
+ tx_inverted_100 = <0x1>;
+ tx_inverted_1000 = <0x1>;
+ };
+};
+
+&gmac1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ tx_delay_sel_fe = <5>;
+ tx_delay_sel = <0>;
+ rxc_dly_en = <0>;
+ tx_inverted_10 = <0x1>;
+ tx_inverted_100 = <0x1>;
+ tx_inverted_1000 = <0x0>;
+ };
+};
+
+&gpu {
+ status = "okay";
+};
+
+&pwmdac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwmdac0_pins>;
+ status = "okay";
+};
+
+&i2srx_3ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_clk_pins &i2srx_pins>;
+ status = "disabled";
+};
+
+&i2stx_4ch1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2stx_pins>;
+ status = "disabled";
+};
+
+&pwmdac_codec {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ssp0_pins>;
+ status = "okay";
+
+ spi_dev0: spi@0 {
+ compatible = "rohm,dh2228fv";
+ pl022,com-mode = <1>;
+ spi-max-frequency = <10000000>;
+ reg = <0>;
+ status = "okay";
+ };
+};
+
+&pcie0 {
+ pinctrl-names = "default", "perst-default", "perst-active";
+ pinctrl-0 = <&pcie0_wake_default>,
+ <&pcie0_clkreq_default>;
+ pinctrl-1 = <&pcie0_perst_default>;
+ pinctrl-2 = <&pcie0_perst_active>;
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default", "perst-default", "perst-active";
+ pinctrl-0 = <&pcie1_wake_default>,
+ <&pcie1_clkreq_default>;
+ pinctrl-1 = <&pcie1_perst_default>;
+ pinctrl-2 = <&pcie1_perst_active>;
+ status = "okay";
+};
+
+&mailbox_contrl0 {
+ status = "okay";
+};
+
+&mailbox_client0 {
+ status = "okay";
+};
+
+&display {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+
+ hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi_in_lcdc: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc_out_dpi1>;
+ };
+ };
+};
+
+&dc8200 {
+ status = "okay";
+
+ dc_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dc_out_dpi0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_input0>;
+ };
+ dc_out_dpi1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_lcdc>;
+ };
+
+ dc_out_dpi2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&mipi_in>;
+ };
+ };
+};
+
+&rgb_output {
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ hdmi_input0:endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc_out_dpi0>;
+ };
+ };
+ };
+};
+
+&dsi_output {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mipi_in: endpoint {
+ remote-endpoint = <&dc_out_dpi2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ sf_dpi_output: endpoint {
+ remote-endpoint = <&dsi_in_port>;
+ };
+ };
+ };
+};
+
+&mipi_dsi {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi0_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_out0>;
+ };
+
+ dsi1_output: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&panel_out1>;
+ };
+ };
+
+ port@1{
+ reg = <1>;
+ dsi_in_port: endpoint {
+ remote-endpoint = <&sf_dpi_output>;
+ };
+ };
+
+ };
+};
+
+&mipi_dphy {
+ status = "okay";
+};
+
+&co_process {
+ status = "okay";
+};
+
+&usbdrd30 {
+ clocks = <&clkgen JH7110_USB_125M>,
+ <&clkgen JH7110_USB0_CLK_APP_125>,
+ <&clkgen JH7110_USB0_CLK_LPM>,
+ <&clkgen JH7110_USB0_CLK_STB>,
+ <&clkgen JH7110_USB0_CLK_USB_APB>,
+ <&clkgen JH7110_USB0_CLK_AXI>,
+ <&clkgen JH7110_USB0_CLK_UTMI_APB>;
+ clock-names = "125m","app","lpm","stb","apb","axi","utmi";
+ resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
+ <&rstgen RSTN_U0_CDN_USB_APB>,
+ <&rstgen RSTN_U0_CDN_USB_AXI>,
+ <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
+ reset-names = "pwrup","apb","axi","utmi";
+ starfive,usb2-only;
+ dr_mode = "peripheral"; /*host or peripheral*/
+ status = "okay";
+};
+
+&xrp {
+ status = "okay";
+};
+
+&ptc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
"ptp_ref",
"stmmaceth",
"pclk",
- "gtxc";
+ "gtxc",
+ "rmii_rtx";
clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
<&clkgen JH7110_U0_GMAC5_CLK_TX>,
<&clkgen JH7110_GMAC0_PTP>,
<&clkgen JH7110_U0_GMAC5_CLK_AHB>,
<&clkgen JH7110_U0_GMAC5_CLK_AXI>,
- <&clkgen JH7110_GMAC0_GTXC>;
+ <&clkgen JH7110_GMAC0_GTXC>,
+ <&clkgen JH7110_GMAC0_RMII_RTX>;
resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
<&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
reset-names = "ahb", "stmmaceth";
"ptp_ref",
"stmmaceth",
"pclk",
- "gtxc";
+ "gtxc",
+ "rmii_rtx";
clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
<&clkgen JH7110_GMAC5_CLK_TX>,
<&clkgen JH7110_GMAC5_CLK_PTP>,
<&clkgen JH7110_GMAC5_CLK_AHB>,
<&clkgen JH7110_GMAC5_CLK_AXI>,
- <&clkgen JH7110_GMAC1_GTXC>;
+ <&clkgen JH7110_GMAC1_GTXC>,
+ <&clkgen JH7110_GMAC1_RMII_RTX>;
resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
<&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
reset-names = "ahb", "stmmaceth";
phy-names = "dphy";
status = "disabled";
- port {
- dsi_out_port: endpoint@0 {
- remote-endpoint = <&panel_dsi_port>;
- };
- dsi_in_port: endpoint@1 {
- remote-endpoint = <&mipi_out>;
- };
- };
-
- mipi_panel: panel@0 {
- /*compatible = "";*/
- status = "okay";
- };
};
hdmi: hdmi@29590000 {
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_STARFIVE_JH7110) += vf2-overlay-uart3-i2c.dtbo
--- /dev/null
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
+/ {
+ compatible = "starfive,visionfive-v2", "starfive,jh7110";
+
+ //gpio
+ fragment@0 {
+ target-path = "/soc/gpio@13040000";
+ __overlay__ {
+ dt_uart3_pins: dt-uart3-pins {
+ uart3-pins-tx {
+ starfive,pins = <PAD_GPIO60>;
+ starfive,pinmux = <PAD_GPIO60_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_UART3_SOUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ uart3-pins-rx {
+ starfive,pins = <PAD_GPIO63>;
+ starfive,pinmux = <PAD_GPIO63_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_UART3_SIN>;
+ };
+ };
+
+ dt_i2c1_pins: dt-i2c1-pins {
+ i2c1-pins-scl {
+ starfive,pins = <PAD_GPIO42>;
+ starfive,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C1_IC_CLK_OE>;
+ starfive,pin-gpio-din = <GPI_I2C1_IC_CLK_IN_A>;
+ };
+
+ i2c1-pins-sda {
+ starfive,pins = <PAD_GPIO43>;
+ starfive,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ starfive,pin-gpio-dout = <GPO_LOW>;
+ starfive,pin-gpio-doen = <OEN_I2C1_IC_DATA_OE>;
+ starfive,pin-gpio-din = <GPI_I2C1_IC_DATA_IN_A>;
+ };
+ };
+ };
+ };
+
+ //uart3
+ fragment@1 {
+ target-path = "/soc/serial@12000000";
+ __overlay__ {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dt_uart3_pins>;
+ status = "okay";
+ };
+ };
+
+ //i2c1
+ fragment@2 {
+ target-path = "/soc/i2c@10040000";
+ __overlay__ {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ auto_calc_scl_lhcnt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dt_i2c1_pins>;
+ status = "okay";
+ };
+ };
+};
+
+
--- /dev/null
+CONFIG_DEFAULT_HOSTNAME="StarFive"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_USELIB=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_CGROUP_BPF=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_SOC_STARFIVE=y
+CONFIG_SOC_STARFIVE_JH7110=y
+CONFIG_SMP=y
+CONFIG_HZ_100=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_CPU_IDLE=y
+CONFIG_RISCV_SBI_CPUIDLE=y
+# CONFIG_SECCOMP is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_CMA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_NETLINK_ACCT=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_TABLES=y
+CONFIG_NFT_CT=y
+CONFIG_NFT_COMPAT=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NFT_DUP_IPV4=y
+CONFIG_NFT_FIB_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_CAN=y
+CONFIG_IPMS_CAN=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_PCI=y
+# CONFIG_PCIEASPM is not set
+CONFIG_PCIE_PLDA=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_OF_CONFIGFS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_EEPROM_AT24=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_SCSI_VIRTIO=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_NETDEVICES=y
+CONFIG_VIRTIO_NET=y
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+CONFIG_R8169=y
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_SELFTESTS=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_STARFIVE_PLAT=y
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_IWLWIFI=y
+CONFIG_IWLDVM=y
+CONFIG_IWLMVM=y
+# CONFIG_RTL_CARDS is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_TTY_PRINTK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_CADENCE_QUADSPI=y
+CONFIG_SPI_PL022_STARFIVE=y
+CONFIG_SPI_SIFIVE=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_STARFIVE=y
+CONFIG_PINCTRL_STARFIVE_JH7110=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_SENSORS_SFCTEMP=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_STARFIVE_WATCHDOG=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_AXP15060=y
+# CONFIG_MEDIA_CEC_SUPPORT is not set
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_STF_VIN=y
+CONFIG_VIN_SENSOR_IMX219=y
+CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=y
+CONFIG_DRM_VERISILICON=y
+CONFIG_STARFIVE_INNO_HDMI=y
+CONFIG_STARFIVE_DSI=y
+CONFIG_DRM_IMG_ROGUE=y
+# CONFIG_DRM_IMG_NULLDISP is not set
+CONFIG_DRM_LEGACY=y
+CONFIG_FB=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_SND_DESIGNWARE_I2S=y
+CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110=y
+CONFIG_SND_SOC_STARFIVE=y
+CONFIG_SND_SOC_STARFIVE_PWMDAC=y
+CONFIG_SND_SOC_STARFIVE_I2S=y
+CONFIG_SND_SOC_AC108=y
+CONFIG_SND_SOC_WM8960=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_UAS=y
+CONFIG_USB_CDNS_SUPPORT=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3_STARFIVE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_STARFIVE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_STARFIVE=y
+CONFIG_RTC_DRV_GOLDFISH=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_AXI_DMAC=y
+CONFIG_DMATEST=y
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_VHOST_MENU is not set
+CONFIG_GOLDFISH=y
+CONFIG_CLK_STARFIVE_JH7110_PLL=y
+CONFIG_STARFIVE_TIMER=y
+CONFIG_MAILBOX=y
+CONFIG_STARFIVE_MBOX=m
+CONFIG_STARFIVE_MBOX_TEST=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_VIRTIO=y
+CONFIG_SIFIVE_L2_FLUSH_START=0x40000000
+CONFIG_SIFIVE_L2_FLUSH_SIZE=0x400000000
+CONFIG_STARFIVE_PMU=y
+CONFIG_PWM=y
+CONFIG_PWM_STARFIVE_PTC=y
+CONFIG_PHY_M31_DPHY_RX0=y
+CONFIG_RAS=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_VIRTIO_FS=y
+CONFIG_OVERLAY_FS=y
+CONFIG_OVERLAY_FS_INDEX=y
+CONFIG_OVERLAY_FS_XINO_AUTO=y
+CONFIG_OVERLAY_FS_METACOPY=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_UTF8=y
+CONFIG_EXFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=y
+CONFIG_CRYPTO_USER_API_AEAD=y
+CONFIG_CRYPTO_USER_API_AKCIPHER=y
+CONFIG_CRYPTO_DEV_VIRTIO=y
+CONFIG_CRYPTO_DEV_JH7110_ENCRYPT=y
+CONFIG_DMA_CMA=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_WQ_WATCHDOG=y
+CONFIG_DEBUG_TIMEKEEPING=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_RWSEMS=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_STACKTRACE=y
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_PLIST=y
+CONFIG_DEBUG_SG=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_EQS_DEBUG=y
+# CONFIG_FTRACE is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_MEMTEST=y
24 bit RGB per pixel. It provides a MIPI DSI interface to
the host and has a built-in LED backlight.
+config DRM_PANEL_JADARD_JD9365DA_H3
+ tristate "Jadard JD9365DA-H3 WUXGA DSI panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for Jadard JD9365DA-H3
+ WUXGA MIPI DSI panel. The panel support TFT dot matrix LCD with
+ 800RGBx1280 dots at maximum.
+
config DRM_PANEL_JDI_LT070ME05000
tristate "JDI LT070ME05000 WUXGA DSI panel"
depends on OF
obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
+obj-$(CONFIG_DRM_PANEL_JADARD_JD9365DA_H3) += panel-jadard-jd9365da-h3.o
obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o
obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ *
+ * Author:
+ * - Jagan Teki <jagan@amarulasolutions.com>
+ * - Stephen Chen <stephen@radxa.com>
+ */
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+
+#include <linux/gpio/consumer.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regulator/consumer.h>
+
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
+#include <video/display_timing.h>
+#include <video/videomode.h>
+
+#define DSI_DRIVER_NAME "starfive-dri"
+
+enum cmd_type {
+ CMD_TYPE_DCS,
+ CMD_TYPE_DELAY,
+};
+
+struct jadard_init_cmd {
+ enum cmd_type type;
+ const char *data;
+ size_t len;
+};
+
+#define _INIT_CMD_DCS(...) \
+ { \
+ .type = CMD_TYPE_DCS, \
+ .data = (char[]){__VA_ARGS__}, \
+ .len = sizeof((char[]){__VA_ARGS__}) \
+ } \
+
+#define _INIT_CMD_DELAY(...) \
+ { \
+ .type = CMD_TYPE_DELAY, \
+ .data = (char[]){__VA_ARGS__}, \
+ .len = sizeof((char[]){__VA_ARGS__}) \
+ } \
+
+struct jadard_panel_desc {
+ const struct drm_display_mode mode;
+ unsigned int lanes;
+ enum mipi_dsi_pixel_format format;
+ const struct jadard_init_cmd *init_cmds;
+ u32 num_init_cmds;
+ const struct display_timing *timings;
+ unsigned int num_timings;
+};
+
+struct jadard {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+ const struct jadard_panel_desc *desc;
+ struct i2c_client *client;
+
+ struct device *dev;
+
+ struct regulator *vdd;
+ struct regulator *vccio;
+ struct gpio_desc *reset;
+ struct gpio_desc *enable;
+ bool enable_initialized;
+};
+
+static inline struct jadard *panel_to_jadard(struct drm_panel *panel)
+{
+ return container_of(panel, struct jadard, panel);
+}
+
+static int jadard_i2c_write(struct i2c_client *client, u8 reg, u8 val)
+{
+ struct i2c_msg msg;
+ u8 buf[2];
+ int ret;
+
+ buf[0] = reg;
+ buf[1] = val;
+ msg.addr = client->addr;
+ msg.flags = 0;
+ msg.buf = buf;
+ msg.len = 2;
+
+ ret = i2c_transfer(client->adapter, &msg, 1);
+ if (ret >= 0)
+ return 0;
+
+ return ret;
+}
+
+static int jadard_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
+{
+ struct i2c_msg msg[2];
+ u8 buf[2];
+ int ret;
+
+ buf[0] = reg;
+ msg[0].addr = client->addr;
+ msg[0].flags = 0;
+ msg[0].buf = buf;
+ msg[0].len = 1;
+ msg[1].addr = client->addr;
+ msg[1].flags = I2C_M_RD;
+ msg[1].buf = val;
+ msg[1].len = 1;
+ ret = i2c_transfer(client->adapter, msg, 2);
+
+ if (ret >= 0)
+ return 0;
+
+ return ret;
+}
+
+static int jadard_enable(struct drm_panel *panel)
+{
+ struct device *dev = panel->dev;
+ struct jadard *jadard = panel_to_jadard(panel);
+ const struct jadard_panel_desc *desc = jadard->desc;
+ struct mipi_dsi_device *dsi = jadard->dsi;
+ unsigned int i;
+ int err;
+ if (jadard->enable_initialized == true)
+ return 0;
+
+ for (i = 0; i < desc->num_init_cmds; i++) {
+ const struct jadard_init_cmd *cmd = &desc->init_cmds[i];
+
+ switch (cmd->type) {
+ case CMD_TYPE_DELAY:
+ msleep(cmd->data[0]);
+ err = 0;
+ break;
+ case CMD_TYPE_DCS:
+ err = mipi_dsi_dcs_write(dsi, cmd->data[0],
+ cmd->len <= 1 ? NULL : &cmd->data[1],
+ cmd->len - 1);
+ break;
+ default:
+ err = -EINVAL;
+ }
+
+ if (err < 0) {
+ DRM_DEV_ERROR(dev, "failed to write CMD#0x%x\n", cmd->data[0]);
+ return err;
+ }
+
+ }
+
+ err = mipi_dsi_dcs_exit_sleep_mode(dsi);
+ if (err < 0)
+ DRM_DEV_ERROR(dev, "failed to exit sleep mode ret = %d\n", err);
+ msleep(120);
+
+ err = mipi_dsi_dcs_set_display_on(dsi);
+ if (err < 0)
+ DRM_DEV_ERROR(dev, "failed to set display on ret = %d\n", err);
+ jadard->enable_initialized = true ;
+
+ return 0;
+}
+
+static int jadard_disable(struct drm_panel *panel)
+{
+ struct device *dev = panel->dev;
+ struct jadard *jadard = panel_to_jadard(panel);
+ int ret;
+
+ ret = mipi_dsi_dcs_set_display_off(jadard->dsi);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret);
+
+ ret = mipi_dsi_dcs_enter_sleep_mode(jadard->dsi);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret);
+
+ jadard->enable_initialized = false;
+
+ return 0;
+}
+
+static int jadard_prepare(struct drm_panel *panel)
+{
+ struct device *dev = panel->dev;
+ struct jadard *jadard = panel_to_jadard(panel);
+ const struct jadard_panel_desc *desc = jadard->desc;
+ struct mipi_dsi_device *dsi = jadard->dsi;
+ unsigned int i;
+ int err;
+
+ if (jadard->enable_initialized == true)
+ return 0;
+
+ gpiod_direction_output(jadard->enable, 0);
+ gpiod_set_value(jadard->enable, 1);
+ mdelay(100);
+
+ gpiod_direction_output(jadard->reset, 0);
+ mdelay(100);
+ gpiod_set_value(jadard->reset, 1);
+ mdelay(100);
+ gpiod_set_value(jadard->reset, 0);
+ mdelay(100);
+ gpiod_set_value(jadard->reset, 1);
+ mdelay(150);
+
+ return 0;
+}
+
+static int jadard_unprepare(struct drm_panel *panel)
+{
+ struct jadard *jadard = panel_to_jadard(panel);
+
+ gpiod_set_value(jadard->reset, 1);
+ msleep(120);
+#if 0
+ regulator_disable(jadard->vdd);
+ regulator_disable(jadard->vccio);
+#endif
+ return 0;
+}
+
+static int jadard_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ struct jadard *jadard = panel_to_jadard(panel);
+ const struct drm_display_mode *desc_mode = &jadard->desc->mode;
+ struct drm_display_mode *mode;
+
+ mode = drm_mode_duplicate(connector->dev, desc_mode);
+ if (!mode) {
+ DRM_DEV_ERROR(&jadard->dsi->dev, "failed to add mode %ux%ux@%u\n",
+ desc_mode->hdisplay, desc_mode->vdisplay,
+ drm_mode_vrefresh(desc_mode));
+ return -ENOMEM;
+ }
+
+ drm_mode_set_name(mode);
+ drm_mode_probed_add(connector, mode);
+
+ connector->display_info.width_mm = mode->width_mm;
+ connector->display_info.height_mm = mode->height_mm;
+
+ return 1;
+}
+
+static int seiko_panel_get_timings(struct drm_panel *panel,
+ unsigned int num_timings,
+ struct display_timing *timings)
+{
+ struct jadard *jadard = panel_to_jadard(panel);
+ unsigned int i;
+
+ if (jadard->desc->num_timings < num_timings)
+ num_timings = jadard->desc->num_timings;
+
+ if (timings)
+ for (i = 0; i < num_timings; i++)
+ timings[i] = jadard->desc->timings[i];
+
+ return jadard->desc->num_timings;
+}
+
+static const struct drm_panel_funcs jadard_funcs = {
+ .disable = jadard_disable,
+ .unprepare = jadard_unprepare,
+ .prepare = jadard_prepare,
+ .enable = jadard_enable,
+ .get_modes = jadard_get_modes,
+ .get_timings = seiko_panel_get_timings,
+};
+
+static const struct jadard_init_cmd cz101b4001_init_cmds[] = {
+ _INIT_CMD_DCS(0x01),
+ _INIT_CMD_DELAY(100),
+ _INIT_CMD_DCS(0xE0, 0x00),
+ _INIT_CMD_DCS(0xE1, 0x93),
+ _INIT_CMD_DCS(0xE2, 0x65),
+ _INIT_CMD_DCS(0xE3, 0xF8),
+ _INIT_CMD_DCS(0x80, 0x03),
+ _INIT_CMD_DCS(0xE0, 0x01),
+ _INIT_CMD_DCS(0x00, 0x00),
+ _INIT_CMD_DCS(0x01, 0x7E),
+ _INIT_CMD_DCS(0x03, 0x00),
+ _INIT_CMD_DCS(0x04, 0x65),
+ _INIT_CMD_DCS(0x0C, 0x74),
+ _INIT_CMD_DCS(0x17, 0x00),
+ _INIT_CMD_DCS(0x18, 0xB7),
+ _INIT_CMD_DCS(0x19, 0x00),
+ _INIT_CMD_DCS(0x1A, 0x00),
+ _INIT_CMD_DCS(0x1B, 0xB7),
+ _INIT_CMD_DCS(0x1C, 0x00),
+ _INIT_CMD_DCS(0x24, 0xFE),
+ _INIT_CMD_DCS(0x37, 0x19),
+ _INIT_CMD_DCS(0x38, 0x05),
+ _INIT_CMD_DCS(0x39, 0x00),
+ _INIT_CMD_DCS(0x3A, 0x01),
+ _INIT_CMD_DCS(0x3B, 0x01),
+ _INIT_CMD_DCS(0x3C, 0x70),
+ _INIT_CMD_DCS(0x3D, 0xFF),
+ _INIT_CMD_DCS(0x3E, 0xFF),
+ _INIT_CMD_DCS(0x3F, 0xFF),
+ _INIT_CMD_DCS(0x40, 0x06),
+ _INIT_CMD_DCS(0x41, 0xA0),
+ _INIT_CMD_DCS(0x43, 0x1E),
+ _INIT_CMD_DCS(0x44, 0x0F),
+ _INIT_CMD_DCS(0x45, 0x28),
+ _INIT_CMD_DCS(0x4B, 0x04),
+ _INIT_CMD_DCS(0x55, 0x02),
+ _INIT_CMD_DCS(0x56, 0x01),
+ _INIT_CMD_DCS(0x57, 0xA9),
+ _INIT_CMD_DCS(0x58, 0x0A),
+ _INIT_CMD_DCS(0x59, 0x0A),
+ _INIT_CMD_DCS(0x5A, 0x37),
+ _INIT_CMD_DCS(0x5B, 0x19),
+ _INIT_CMD_DCS(0x5D, 0x78),
+ _INIT_CMD_DCS(0x5E, 0x63),
+ _INIT_CMD_DCS(0x5F, 0x54),
+ _INIT_CMD_DCS(0x60, 0x49),
+ _INIT_CMD_DCS(0x61, 0x45),
+ _INIT_CMD_DCS(0x62, 0x38),
+ _INIT_CMD_DCS(0x63, 0x3D),
+ _INIT_CMD_DCS(0x64, 0x28),
+ _INIT_CMD_DCS(0x65, 0x43),
+ _INIT_CMD_DCS(0x66, 0x41),
+ _INIT_CMD_DCS(0x67, 0x43),
+ _INIT_CMD_DCS(0x68, 0x62),
+ _INIT_CMD_DCS(0x69, 0x50),
+ _INIT_CMD_DCS(0x6A, 0x57),
+ _INIT_CMD_DCS(0x6B, 0x49),
+ _INIT_CMD_DCS(0x6C, 0x44),
+ _INIT_CMD_DCS(0x6D, 0x37),
+ _INIT_CMD_DCS(0x6E, 0x23),
+ _INIT_CMD_DCS(0x6F, 0x10),
+ _INIT_CMD_DCS(0x70, 0x78),
+ _INIT_CMD_DCS(0x71, 0x63),
+ _INIT_CMD_DCS(0x72, 0x54),
+ _INIT_CMD_DCS(0x73, 0x49),
+ _INIT_CMD_DCS(0x74, 0x45),
+ _INIT_CMD_DCS(0x75, 0x38),
+ _INIT_CMD_DCS(0x76, 0x3D),
+ _INIT_CMD_DCS(0x77, 0x28),
+ _INIT_CMD_DCS(0x78, 0x43),
+ _INIT_CMD_DCS(0x79, 0x41),
+ _INIT_CMD_DCS(0x7A, 0x43),
+ _INIT_CMD_DCS(0x7B, 0x62),
+ _INIT_CMD_DCS(0x7C, 0x50),
+ _INIT_CMD_DCS(0x7D, 0x57),
+ _INIT_CMD_DCS(0x7E, 0x49),
+ _INIT_CMD_DCS(0x7F, 0x44),
+ _INIT_CMD_DCS(0x80, 0x37),
+ _INIT_CMD_DCS(0x81, 0x23),
+ _INIT_CMD_DCS(0x82, 0x10),
+ _INIT_CMD_DCS(0xE0, 0x02),
+ _INIT_CMD_DCS(0x00, 0x47),
+ _INIT_CMD_DCS(0x01, 0x47),
+ _INIT_CMD_DCS(0x02, 0x45),
+ _INIT_CMD_DCS(0x03, 0x45),
+ _INIT_CMD_DCS(0x04, 0x4B),
+ _INIT_CMD_DCS(0x05, 0x4B),
+ _INIT_CMD_DCS(0x06, 0x49),
+ _INIT_CMD_DCS(0x07, 0x49),
+ _INIT_CMD_DCS(0x08, 0x41),
+ _INIT_CMD_DCS(0x09, 0x1F),
+ _INIT_CMD_DCS(0x0A, 0x1F),
+ _INIT_CMD_DCS(0x0B, 0x1F),
+ _INIT_CMD_DCS(0x0C, 0x1F),
+ _INIT_CMD_DCS(0x0D, 0x1F),
+ _INIT_CMD_DCS(0x0E, 0x1F),
+ _INIT_CMD_DCS(0x0F, 0x5F),
+ _INIT_CMD_DCS(0x10, 0x5F),
+ _INIT_CMD_DCS(0x11, 0x57),
+ _INIT_CMD_DCS(0x12, 0x77),
+ _INIT_CMD_DCS(0x13, 0x35),
+ _INIT_CMD_DCS(0x14, 0x1F),
+ _INIT_CMD_DCS(0x15, 0x1F),
+ _INIT_CMD_DCS(0x16, 0x46),
+ _INIT_CMD_DCS(0x17, 0x46),
+ _INIT_CMD_DCS(0x18, 0x44),
+ _INIT_CMD_DCS(0x19, 0x44),
+ _INIT_CMD_DCS(0x1A, 0x4A),
+ _INIT_CMD_DCS(0x1B, 0x4A),
+ _INIT_CMD_DCS(0x1C, 0x48),
+ _INIT_CMD_DCS(0x1D, 0x48),
+ _INIT_CMD_DCS(0x1E, 0x40),
+ _INIT_CMD_DCS(0x1F, 0x1F),
+ _INIT_CMD_DCS(0x20, 0x1F),
+ _INIT_CMD_DCS(0x21, 0x1F),
+ _INIT_CMD_DCS(0x22, 0x1F),
+ _INIT_CMD_DCS(0x23, 0x1F),
+ _INIT_CMD_DCS(0x24, 0x1F),
+ _INIT_CMD_DCS(0x25, 0x5F),
+ _INIT_CMD_DCS(0x26, 0x5F),
+ _INIT_CMD_DCS(0x27, 0x57),
+ _INIT_CMD_DCS(0x28, 0x77),
+ _INIT_CMD_DCS(0x29, 0x35),
+ _INIT_CMD_DCS(0x2A, 0x1F),
+ _INIT_CMD_DCS(0x2B, 0x1F),
+ _INIT_CMD_DCS(0x58, 0x40),
+ _INIT_CMD_DCS(0x59, 0x00),
+ _INIT_CMD_DCS(0x5A, 0x00),
+ _INIT_CMD_DCS(0x5B, 0x10),
+ _INIT_CMD_DCS(0x5C, 0x06),
+ _INIT_CMD_DCS(0x5D, 0x40),
+ _INIT_CMD_DCS(0x5E, 0x01),
+ _INIT_CMD_DCS(0x5F, 0x02),
+ _INIT_CMD_DCS(0x60, 0x30),
+ _INIT_CMD_DCS(0x61, 0x01),
+ _INIT_CMD_DCS(0x62, 0x02),
+ _INIT_CMD_DCS(0x63, 0x03),
+ _INIT_CMD_DCS(0x64, 0x6B),
+ _INIT_CMD_DCS(0x65, 0x05),
+ _INIT_CMD_DCS(0x66, 0x0C),
+ _INIT_CMD_DCS(0x67, 0x73),
+ _INIT_CMD_DCS(0x68, 0x09),
+ _INIT_CMD_DCS(0x69, 0x03),
+ _INIT_CMD_DCS(0x6A, 0x56),
+ _INIT_CMD_DCS(0x6B, 0x08),
+ _INIT_CMD_DCS(0x6C, 0x00),
+ _INIT_CMD_DCS(0x6D, 0x04),
+ _INIT_CMD_DCS(0x6E, 0x04),
+ _INIT_CMD_DCS(0x6F, 0x88),
+ _INIT_CMD_DCS(0x70, 0x00),
+ _INIT_CMD_DCS(0x71, 0x00),
+ _INIT_CMD_DCS(0x72, 0x06),
+ _INIT_CMD_DCS(0x73, 0x7B),
+ _INIT_CMD_DCS(0x74, 0x00),
+ _INIT_CMD_DCS(0x75, 0xF8),
+ _INIT_CMD_DCS(0x76, 0x00),
+ _INIT_CMD_DCS(0x77, 0xD5),
+ _INIT_CMD_DCS(0x78, 0x2E),
+ _INIT_CMD_DCS(0x79, 0x12),
+ _INIT_CMD_DCS(0x7A, 0x03),
+ _INIT_CMD_DCS(0x7B, 0x00),
+ _INIT_CMD_DCS(0x7C, 0x00),
+ _INIT_CMD_DCS(0x7D, 0x03),
+ _INIT_CMD_DCS(0x7E, 0x7B),
+ _INIT_CMD_DCS(0xE0, 0x04),
+ _INIT_CMD_DCS(0x00, 0x0E),
+ _INIT_CMD_DCS(0x02, 0xB3),
+ _INIT_CMD_DCS(0x09, 0x60),
+ _INIT_CMD_DCS(0x0E, 0x2A),
+ _INIT_CMD_DCS(0x36, 0x59),
+ _INIT_CMD_DCS(0xE0, 0x00),
+
+ _INIT_CMD_DELAY(120),
+};
+
+static const struct display_timing jadard_timing = {
+ .pixelclock = { 79200000, 79200000, 79200000 },
+ .hactive = { 800, 800, 800 },
+ .hfront_porch = { 356, 356, 356 },
+ .hback_porch = { 134, 134, 134 },
+ .hsync_len = { 7, 7, 7 },
+ .vactive = { 1280, 1280, 1280 },
+ .vfront_porch = { 84, 84, 84 },
+ .vback_porch = { 20, 20, 20 },
+ .vsync_len = { 9, 9, 9 },
+ .flags = DISPLAY_FLAGS_DE_LOW,
+};
+
+static const struct jadard_panel_desc cz101b4001_desc = {
+ .mode = {
+ .clock = 79200,
+
+ .hdisplay = 800,
+ .hsync_start = 800 + 139,
+ .hsync_end = 800 + 139 + 5,
+ .htotal = 800 + 139 + 5 + 5,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 84,
+ .vsync_end = 1280 + 84 + 20,
+ .vtotal = 1280 + 84+ 20 + 7,
+
+ .width_mm = 62,
+ .height_mm = 110,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .lanes = 4,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init_cmds = cz101b4001_init_cmds,
+ .num_init_cmds = ARRAY_SIZE(cz101b4001_init_cmds),
+ .timings = &jadard_timing,
+ .num_timings = 1,
+};
+
+static int panel_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+ u8 reg_value = 0;
+ struct jadard *jd_panel;
+ const struct jadard_panel_desc *desc;
+
+ struct device_node *endpoint, *dsi_host_node;
+ struct mipi_dsi_host *host;
+ struct device *dev = &client->dev;
+ int ret = 0;
+ struct mipi_dsi_device_info info = {
+ .type = DSI_DRIVER_NAME,
+ .channel = 1, //0,
+ .node = NULL,
+ };
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ dev_warn(&client->dev,
+ "I2C adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
+ return -EIO;
+ }
+
+ jd_panel = devm_kzalloc(&client->dev, sizeof(struct jadard), GFP_KERNEL);
+ if (!jd_panel )
+ return -ENOMEM;
+ desc = of_device_get_match_data(dev);
+
+ jd_panel ->client = client;
+ i2c_set_clientdata(client, jd_panel);
+
+ jd_panel->enable_initialized = false;
+
+ jd_panel->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(jd_panel->reset)) {
+ DRM_DEV_ERROR(dev, "failed to get our reset GPIO\n");
+ return PTR_ERR(jd_panel->reset);
+ }
+
+ jd_panel->enable = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
+ if (IS_ERR(jd_panel->enable)) {
+ DRM_DEV_ERROR(dev, "failed to get our enable GPIO\n");
+ return PTR_ERR(jd_panel->enable);
+ }
+
+ /*use i2c read to detect whether the panel has connected */
+ ret = jadard_i2c_read(client, 0x00, ®_value);
+ if (ret < 0)
+ return -ENODEV;
+
+ endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+ if (!endpoint)
+ return -ENODEV;
+
+ dsi_host_node = of_graph_get_remote_port_parent(endpoint);
+ if (!dsi_host_node)
+ goto error;
+
+ host = of_find_mipi_dsi_host_by_node(dsi_host_node);
+ of_node_put(dsi_host_node);
+ if (!host) {
+ of_node_put(endpoint);
+ return -EPROBE_DEFER;
+ }
+
+ drm_panel_init(&jd_panel->panel, dev, &jadard_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+
+ drm_panel_add(&jd_panel->panel);
+
+ info.node = of_node_get(of_graph_get_remote_port(endpoint));
+ if (!info.node)
+ goto error;
+
+ of_node_put(endpoint);
+ jd_panel->desc = desc;
+
+ jd_panel->dsi = mipi_dsi_device_register_full(host, &info);
+ if (IS_ERR(jd_panel->dsi)) {
+ dev_err(dev, "DSI device registration failed: %ld\n",
+ PTR_ERR(jd_panel->dsi));
+ return PTR_ERR(jd_panel->dsi);
+ }
+
+ mipi_dsi_set_drvdata(jd_panel->dsi, jd_panel);
+
+ return 0;
+error:
+ of_node_put(endpoint);
+ return -ENODEV;
+no_panel:
+ mipi_dsi_device_unregister(jd_panel->dsi);
+ //drm_panel_remove(&jd_panel->panel);
+ //mipi_dsi_detach(jd_panel->dsi);
+
+ return -ENODEV;
+
+
+}
+
+static int panel_remove(struct i2c_client *client)
+{
+ struct jadard *jd_panel = i2c_get_clientdata(client);
+
+ mipi_dsi_detach(jd_panel->dsi);
+ drm_panel_remove(&jd_panel->panel);
+ mipi_dsi_device_unregister(jd_panel->dsi);
+ return 0;
+}
+
+static const struct i2c_device_id panel_id[] = {
+ { "starfive_jadard", 0 },
+ { }
+};
+
+static const struct of_device_id panel_dt_ids[] = {
+ { .compatible = "starfive_jadard", .data = &cz101b4001_desc},
+ { /* sentinel */ }
+};
+
+static struct i2c_driver panel_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "starfive_jadard",
+ .of_match_table = panel_dt_ids,
+ },
+ .probe = panel_probe,
+ .remove = panel_remove,
+ .id_table = panel_id,
+};
+
+static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct jadard *jadard = mipi_dsi_get_drvdata(dsi);
+
+ int ret;
+
+ dsi->mode_flags = MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE ;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->lanes = 4;
+ dsi->channel = 1;
+ dsi->hs_rate = 490000000;
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0) {
+ return ret;
+ }
+
+ return 0;
+}
+
+static int jadard_dsi_remove(struct mipi_dsi_device *dsi)
+{
+ struct jadard *jadard = mipi_dsi_get_drvdata(dsi);
+
+ mipi_dsi_detach(dsi);
+ drm_panel_remove(&jadard->panel);
+
+ return 0;
+}
+
+static const struct of_device_id jadard_of_match[] = {
+ { .compatible = "starfive-dri-panel-1", .data = &cz101b4001_desc },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jadard_of_match);
+
+static struct mipi_dsi_driver jadard_mipi_driver = {
+ .probe = jadard_dsi_probe,
+ .remove = jadard_dsi_remove,
+ .driver.name = DSI_DRIVER_NAME,
+};
+//module_mipi_dsi_driver(jadard_driver);
+
+
+static int __init init_panel(void)
+{
+ int err;
+
+ mipi_dsi_driver_register(&jadard_mipi_driver);
+ err = i2c_add_driver(&panel_driver);
+
+ return err;
+
+}
+module_init(init_panel);
+
+static void __exit exit_panel(void)
+{
+ i2c_del_driver(&panel_driver);
+ mipi_dsi_driver_unregister(&jadard_mipi_driver);
+}
+module_exit(exit_panel);
+
+
+MODULE_AUTHOR("Jagan Teki <jagan@edgeble.ai>");
+MODULE_AUTHOR("Stephen Chen <stephen@radxa.com>");
+MODULE_DESCRIPTION("Jadard JD9365DA-H3 WUXGA DSI panel");
+MODULE_LICENSE("GPL");
+
bpp, DSI_HFP_FRAME_OVERHEAD);
//dpi to dsi transfer can not match , reconfig those parms for waveshare
//for taobao old mipi panel .should change here : hsa 36 , hbp 108, hfp 288
- if (mode->hdisplay == 800) {
+ if (mode->vdisplay == 1280) {
+ dsi_cfg->hsa = 45-DSI_HSA_FRAME_OVERHEAD;
+ dsi_cfg->hbp = 134-DSI_HBP_FRAME_OVERHEAD;
+ dsi_cfg->hfp = 356-DSI_HFP_FRAME_OVERHEAD;
+ }
+ if (mode->vdisplay == 480) {
dsi_cfg->hsa = 117-DSI_HSA_FRAME_OVERHEAD;
dsi_cfg->hbp = 115-DSI_HBP_FRAME_OVERHEAD;
dsi_cfg->hfp = 209-DSI_HFP_FRAME_OVERHEAD;
dpi_htotal = mode_valid_check ? mode->htotal : mode->crtc_htotal;
/* data rate was in bytes/sec, convert to bits/sec. */
- phy_cfg->hs_clk_rate = 750000000;
+ phy_cfg->hs_clk_rate = output->phy_opts.mipi_dphy.hs_clk_rate;
dsi_hfp_ext = adj_dsi_htotal - dsi_htotal;
dsi_cfg->hfp += dsi_hfp_ext;
if (ret)
return ret;
- phy_cfg->hs_clk_rate = 750000000;
+ //phy_cfg->hs_clk_rate = output->phy_opts.mipi_dphy.hs_clk_rate;
+ if (mode->vdisplay == 480)
+ phy_cfg->hs_clk_rate = 750000000;
+ else if (mode->vdisplay == 1280)
+ phy_cfg->hs_clk_rate = 490000000;
+
+ dsi_cfg->htotal = dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD +
+ dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD +
+ dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD + dsi_cfg->hact;
dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;
if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
* Power all internal DPHY blocks down and maintain their reset line
* asserted before changing the DPHY config.
*/
- writel(DPHY_CMN_PSO | DPHY_PLL_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN |
- DPHY_CMN_PDN | DPHY_PLL_PDN,
- dsi->regs + MCTL_DPHY_CFG0);
+ //writel(DPHY_CMN_PSO | DPHY_PLL_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN |
+ // DPHY_CMN_PDN | DPHY_PLL_PDN,
+ // dsi->regs + MCTL_DPHY_CFG0);
+ // Commented by Tony Ren: this is not appliable for our case as it is intended for its own dphy
phy_init(dsi->dphy);
phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
phy_power_on(dsi->dphy);
ret = sys_mipi_dsi_set_ppi_txbyte_hs(1, dsi);
-
+#if 0
writel(PLL_LOCKED, dsi->regs + MCTL_MAIN_STS_CLR);
writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN,
dsi->regs + MCTL_DPHY_CFG0);
writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN |
DPHY_D_RSTB(output->dev->lanes) | DPHY_C_RSTB,
dsi->regs + MCTL_DPHY_CFG0);
-
+#endif
/*
dpi_fifo_int = readl(dsi->regs + DPI_IRQ_CLR);
if (dpi_fifo_int)
static void cdns_dsi_init_link(struct cdns_dsi *dsi)
{
struct cdns_dsi_output *output = &dsi->output;
- unsigned long sysclk_period, ulpout;
+ unsigned long ulpout;
u32 val;
int i;
writel(val, dsi->regs + MCTL_MAIN_PHY_CTL);
- /* ULPOUT should be set to 1ms and is expressed in sysclk cycles.*/
- sysclk_period = NSEC_PER_SEC / clk_get_rate(dsi->dsi_sys_clk);
- ulpout = DIV_ROUND_UP(NSEC_PER_MSEC, sysclk_period);
+ ulpout = DIV_ROUND_UP(clk_get_rate(dsi->dsi_sys_clk), MSEC_PER_SEC);
+
writel(CLK_LANE_ULPOUT_TIME(ulpout) | DATA_LANE_ULPOUT_TIME(ulpout),
dsi->regs + MCTL_ULPOUT_TIME);
writel(LINK_EN, dsi->regs + MCTL_MAIN_DATA_CTL);
- val = CLK_LANE_EN | PLL_START;
+ val = CLK_LANE_EN | CLK_FORCE_STOP ; // | PLL_START; unused bit
for (i = 0; i < output->dev->lanes; i++)
val |= DATA_LANE_START(i);
writel(val, dsi->regs + MCTL_MAIN_EN);
+ udelay(20);
dsi->link_initialized = true;
}
+static void start_clane_hs(struct cdns_dsi *dsi)
+{
+ // struct cdns_dsi *dsi = (struct cdns_dsi *)handle->priv;
+ struct cdns_dsi_output *output = &dsi->output;
+
+ unsigned long ulpout;
+ u32 val;
+ int i;
+
+ val = WAIT_BURST_TIME(0xf);
+ for (i = 1; i < output->dev->lanes; i++)
+ val |= DATA_LANE_EN(i);
+
+ if (!(output->dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
+ val |= CLK_CONTINUOUS;
+
+ writel(val, dsi->regs + MCTL_MAIN_PHY_CTL);
+
+ ulpout = DIV_ROUND_UP(clk_get_rate(dsi->dsi_sys_clk), MSEC_PER_SEC);
+ writel(CLK_LANE_ULPOUT_TIME(ulpout) | DATA_LANE_ULPOUT_TIME(ulpout),
+ dsi->regs + MCTL_ULPOUT_TIME);
+
+ writel(LINK_EN, dsi->regs + MCTL_MAIN_DATA_CTL);
+
+ val = CLK_LANE_EN; // | CLK_FORCE_STOP; // | PLL_START; unused bit
+ for (i = 0; i < output->dev->lanes; i++)
+ val |= DATA_LANE_START(i);
+
+ writel(val, dsi->regs + MCTL_MAIN_EN); // start hs clk lane
+
+ // clane output DDR(Double Data Rate) clock = half of dphy hs_rate, because hs is double edge sampling
+
+ dsi->link_initialized = true;
+}
+
static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
{
struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
//WARN_ON_ONCE(cdns_dsi_check_conf(dsi, mode, &dsi_cfg, false));//original //7110 mode illegal,need confirm //cannot disable
cdns_dsi_check_conf(dsi, mode, &dsi_cfg, false);
-
cdns_dsi_hs_init(dsi);
cdns_dsi_init_link(dsi);
+ if (output->panel)
+ drm_panel_prepare(output->panel);
+
+ if (output->panel)
+ drm_panel_enable(output->panel);
+
writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa),
dsi->regs + VID_HSIZE1);
writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact),
tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8,
phy_cfg->hs_clk_rate);
reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / tx_byte_period;
+
writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),
dsi->regs + VID_DPHY_TIME);
- vrefresh = drm_mode_vrefresh(mode);//display_timing_vrefresh(dpi);
+ vrefresh = drm_mode_vrefresh(mode)-1;//display_timing_vrefresh(dpi);
tmp = NSEC_PER_SEC / vrefresh;
tmp /= tx_byte_period;
writel(tmp, dsi->regs + VID_MAIN_CTL);
}
+ //to restart the clane and dlane
+ start_clane_hs(dsi);
+
tmp = readl(dsi->regs + MCTL_MAIN_DATA_CTL);
tmp &= ~(IF_VID_SELECT_MASK | HOST_EOT_GEN | IF_VID_MODE);
tmp = readl(dsi->regs + MCTL_MAIN_EN) | IF_EN(input->id);
writel(tmp, dsi->regs + MCTL_MAIN_EN);
+
}
static const struct drm_bridge_funcs cdns_dsi_bridge_funcs = {
*/
np = of_graph_get_remote_node(dsi->base.dev->of_node, DSI_OUTPUT_PORT,
dev->channel);
+
if (!np)
np = of_node_get(dev->dev.of_node);
return ret;
}
+
+
static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg)
{
struct cdns_dsi *dsi = to_cdns_dsi(host);
- u32 cmd, val, wait = WRITE_COMPLETED, ctl = 0;
+ u32 cmd, sts, val, wait = WRITE_COMPLETED, ctl = 0;
struct mipi_dsi_packet packet;
int ret, i, tx_len, rx_len;
- u32 stat = 0;
- int timeout = 100;
- int stat_88;
- int stat_188;
- int stat_88_ack_val;
- ret = pm_runtime_get_sync(host->dev);
+ ret = pm_runtime_resume_and_get(host->dev);
if (ret < 0)
return ret;
/* For read operations, the maximum TX len is 2. */
if (rx_len && tx_len > 2) {
- ret = -EOPNOTSUPP;
+ ret = -ENOTSUPP;
goto out;
}
/* TX len is limited by the CMD FIFO depth. */
if (tx_len > dsi->direct_cmd_fifo_depth) {
- ret = -EOPNOTSUPP;
+ ret = -ENOTSUPP;
goto out;
}
/* RX len is limited by the RX FIFO depth. */
if (rx_len > dsi->rx_fifo_depth) {
- ret = -EOPNOTSUPP;
+ ret = -ENOTSUPP;
goto out;
}
ctl = BTA_EN;
}
- /* Clear status flags before sending the command. */
+ writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) | ctl,
+ dsi->regs + MCTL_MAIN_DATA_CTL);
- iowrite32(wait, dsi->regs + DIRECT_CMD_STS_CLR);
- iowrite32(wait, dsi->regs + DIRECT_CMD_STS_CTL);
- iowrite32(cmd, dsi->regs + DIRECT_CMD_MAIN_SETTINGS);
+ writel(cmd, dsi->regs + DIRECT_CMD_MAIN_SETTINGS);
for (i = 0; i < tx_len; i += 4) {
const u8 *buf = msg->tx_buf;
val = 0;
for (j = 0; j < 4 && j + i < tx_len; j++)
val |= (u32)buf[i + j] << (8 * j);
- iowrite32(val, dsi->regs + DIRECT_CMD_WRDATA);
+
+ writel(val, dsi->regs + DIRECT_CMD_WRDATA);
}
- iowrite32(0, dsi->regs + DIRECT_CMD_SEND);
- do {
- stat = readl(dsi->regs + DIRECT_CMD_STS);
- if ((stat & 0x02) == 0x02)
- break;
- mdelay(10);
- } while (--timeout);
- if (!timeout)
- DRM_DEBUG("timeout!\n");
-
- stat_88 = readl(dsi->regs + DIRECT_CMD_STS);
- stat_188 = readl(dsi->regs + MCTL_DPHY_ERR_FLAG);
- stat_88_ack_val = stat_88 >> 16;
- if (stat_188 || stat_88_ack_val)
- dev_dbg(host->dev, "stat: [188h] %08x, [88h] %08x\r\n", stat_188, stat_88);
+ /* Clear status flags before sending the command. */
+ writel(wait, dsi->regs + DIRECT_CMD_STS_CLR);
+ writel(wait, dsi->regs + DIRECT_CMD_STS_CTL);
+ reinit_completion(&dsi->direct_cmd_comp);
+ writel(0, dsi->regs + DIRECT_CMD_SEND);
+
+ wait_for_completion_timeout(&dsi->direct_cmd_comp,
+ msecs_to_jiffies(1000));
+
+ sts = readl(dsi->regs + DIRECT_CMD_STS);
+ writel(wait, dsi->regs + DIRECT_CMD_STS_CLR);
+ writel(0, dsi->regs + DIRECT_CMD_STS_CTL);
+
+ writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) & ~ctl,
+ dsi->regs + MCTL_MAIN_DATA_CTL);
+
+ /* We did not receive the events we were waiting for. */
+ if (!(sts & wait)) {
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ /* 'READ' or 'WRITE with ACK' failed. */
+ if (sts & (READ_COMPLETED_WITH_ERR | ACK_WITH_ERR_RCVD)) {
+ ret = -EIO;
+ goto out;
+ }
+
+ for (i = 0; i < rx_len; i += 4) {
+ u8 *buf = msg->rx_buf;
+ int j;
+
+ val = readl(dsi->regs + DIRECT_CMD_RDDATA);
+ for (j = 0; j < 4 && j + i < rx_len; j++)
+ buf[i + j] = val >> (8 * j);
+ }
out:
pm_runtime_put(host->dev);
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_panel.h>
#include "vs_drv.h"
-#define RPI_DSI_DRIVER_NAME "cdns-dri-panel"
+#define RPI_DSI_DRIVER_NAME "starfive-dri-panel"
/* I2C registers of the Atmel microcontroller. */
enum REG_ADDR {
MIPI_DSI_MODE_LPM);
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->lanes = 1;
+ dsi->hs_rate = 750000000;
ret = mipi_dsi_attach(dsi);
if (ret)
*/
clk_set_parent(dc->dc8200_clk_pix1, dc->dc8200_pix0);
- udelay(1000);
dc_hw_set_out(&dc->hw, OUT_DPI, display.id);
} else {
/*
};
extern struct platform_driver dc_platform_driver;
-extern struct platform_driver starfive_dsi_platform_driver;
-extern int init_seeed_panel(void);
-extern void exit_seeed_panel(void);
+
#endif /* __VS_DC_H__ */
ensure linux/arch/riscv/configs/starfive_jh7110_defconfig:
CONFIG_VIDEO_STF_VIN=y
-CONFIG_VIN_SENSOR_SC2235=y
-CONFIG_VIN_SENSOR_OV4689=y
+CONFIG_VIN_SENSOR_IMX219=y
-Only support the lane0/lane5 of dphy as clock lane, lane1/lane2/lane3/lane4
+Only support the lane4/lane5 of dphy as clock lane, lane0/lane1/lane2/lane3
as data lane.
#include <media/v4l2-event.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-mediabus.h>
-#include <linux/pinctrl/pinctrl.h>
#include <asm/unaligned.h>
#define IMX219_REG_VALUE_08BIT 1
},
};
-struct sensor_pinctrl_info {
- struct pinctrl *pinctrl;
- struct pinctrl_state *power_up;
- struct pinctrl_state *power_down;
- bool use_pinctrl;
-};
-
struct imx219 {
struct v4l2_subdev sd;
struct media_pad pad;
/* Streaming on/off */
int streaming;
-
- struct sensor_pinctrl_info imx219_pctrl;
};
-int imx219_sensor_pinctrl_init(
- struct sensor_pinctrl_info *sensor_pctrl, struct device *dev)
-{
- sensor_pctrl->pinctrl = devm_pinctrl_get(dev);
- if (IS_ERR_OR_NULL(sensor_pctrl->pinctrl)) {
- pr_err("Getting pinctrl handle failed\n");
- return -EINVAL;
- }
-
- sensor_pctrl->power_up
- = pinctrl_lookup_state(sensor_pctrl->pinctrl, "power_up");
- if (IS_ERR_OR_NULL(sensor_pctrl->power_up)) {
- pr_err("Failed to get the power_up pinctrl handle\n");
- return -EINVAL;
- }
-
- sensor_pctrl->power_down
- = pinctrl_lookup_state(sensor_pctrl->pinctrl, "power_down");
- if (IS_ERR_OR_NULL(sensor_pctrl->power_down)) {
- pr_err("Failed to get the power_down pinctrl handle\n");
- return -EINVAL;
- }
-
- sensor_pctrl->use_pinctrl = true;
-
- return 0;
-}
-
static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd)
{
return container_of(_sd, struct imx219, sd);
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx219 *imx219 = to_imx219(sd);
- struct sensor_pinctrl_info *sensor_pctrl = &imx219->imx219_pctrl;
int ret;
ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES, imx219->supplies);
goto reg_off;
}
- if (sensor_pctrl->use_pinctrl) {
- ret = pinctrl_select_state(
- sensor_pctrl->pinctrl,
- sensor_pctrl->power_up);
- if (ret)
- pr_err("cannot set pin to power up\n");
- } else
- gpiod_set_value_cansleep(imx219->reset_gpio, 1);
-
+ gpiod_set_value_cansleep(imx219->reset_gpio, 1);
usleep_range(IMX219_XCLR_MIN_DELAY_US,
IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US);
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx219 *imx219 = to_imx219(sd);
- struct sensor_pinctrl_info *sensor_pctrl = &imx219->imx219_pctrl;
- int ret;
-
- if (sensor_pctrl->use_pinctrl) {
- ret = pinctrl_select_state(
- sensor_pctrl->pinctrl,
- sensor_pctrl->power_down);
- if (ret)
- pr_err("cannot set pin to power_down\n");
- } else
- gpiod_set_value_cansleep(imx219->reset_gpio, 0);
+ gpiod_set_value_cansleep(imx219->reset_gpio, 0);
regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
clk_disable_unprepare(imx219->xclk);
return ret;
}
- ret = imx219_sensor_pinctrl_init(&imx219->imx219_pctrl, dev);
- if (ret) {
- pr_err("Can't get pinctrl, use gpio to ctrl\n");
- /* Request optional enable pin */
- imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
- imx219->imx219_pctrl.use_pinctrl = false;
- }
+ /* Request optional enable pin */
+ imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
/*
* The sensor must be powered for imx219_identify_module()
// #define STF_DEBUG
-// #define USE_CSIDPHY_ONE_CLK_MODE 1
+#define USE_CSIDPHY_ONE_CLK_MODE 1
enum {
ST_DVP = 0x0001,
struct media_pad *pads = csi_dev->pads;
int ret;
- csi_dev->mipirx_1p8 = devm_regulator_get(dev, "mipirx_1p8");
- if (IS_ERR(csi_dev->mipirx_1p8))
- return PTR_ERR(csi_dev->mipirx_1p8);
-
- csi_dev->mipirx_0p9 = devm_regulator_get(dev, "mipirx_0p9");
+ csi_dev->mipirx_0p9 = devm_regulator_get(dev, "mipi_0p9");
if (IS_ERR(csi_dev->mipirx_0p9))
return PTR_ERR(csi_dev->mipirx_0p9);
struct csi_hw_ops *hw_ops;
struct mutex stream_lock;
int stream_count;
- struct regulator *mipirx_1p8;
struct regulator *mipirx_0p9;
};
int ret;
if (on) {
- ret = regulator_enable(csi_dev->mipirx_1p8);
- if (ret) {
- st_err(ST_CSI, "Cannot enable mipirx_1p8 regulator\n");
- goto err_1p8;
- }
-
ret = regulator_enable(csi_dev->mipirx_0p9);
if (ret) {
st_err(ST_CSI, "Cannot enable mipirx_0p9 regulator\n");
- goto err_0p9;
+ return ret;
}
- } else {
- regulator_disable(csi_dev->mipirx_1p8);
+ } else
regulator_disable(csi_dev->mipirx_0p9);
- }
regmap_update_bits(stfcamss->stf_aon_syscon, stfcamss->aon_gp_reg,
BIT(31), BIT(31));
return 0;
-
-err_0p9:
- regulator_disable(csi_dev->mipirx_1p8);
-err_1p8:
- return ret;
-
}
static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
{
int i = 0;
- cfg->clock_lane = 0;
+ cfg->clock_lane = 4;
cfg->clock1_lane = 5;
- cfg->data_lanes[0] = 1;
- cfg->data_lanes[1] = 2;
- cfg->data_lanes[2] = 3;
- cfg->data_lanes[3] = 4;
+ cfg->data_lanes[0] = 0;
+ cfg->data_lanes[1] = 1;
+ cfg->data_lanes[2] = 2;
+ cfg->data_lanes[3] = 3;
if (cfg0 && cfg1) {
st_debug(ST_CSIPHY, "CSIPHY use 2 clk mode\n");
st_debug(ST_CSIPHY, "CSIPHY cfg0 use 1 clk mode\n");
cfg->num_clks = 1;
cfg->num_data_lanes = cfg0->num_data_lanes;
- cfg->clock_lane = cfg->clock1_lane = cfg0->clock_lane;
cfg->lane_polarities[0] = cfg->lane_polarities[1] =
cfg0->lane_polarities[0];
for (i = 0; i < cfg0->num_data_lanes; i++) {
st_debug(ST_CSIPHY, "CSIPHY cfg1 use 1 clk mode\n");
cfg->num_clks = 1;
cfg->num_data_lanes = cfg1->num_data_lanes;
- cfg->clock_lane = cfg->clock1_lane = cfg1->clock_lane;
cfg->lane_polarities[0] = cfg->lane_polarities[1] =
cfg1->lane_polarities[0];
for (i = 0; i < cfg1->num_data_lanes; i++) {
static const struct dw_mci_drv_data starfive_data = {
.caps = dw_mci_starfive_caps,
.num_caps = ARRAY_SIZE(dw_mci_starfive_caps),
- .set_ios = dw_mci_starfive_set_ios,
+ //.set_ios = dw_mci_starfive_set_ios,
.parse_dt = dw_mci_starfive_parse_dt,
.execute_tuning = dw_mci_starfive_execute_tuning,
- .switch_voltage = dw_mci_starfive_switch_voltage,
+ //.switch_voltage = dw_mci_starfive_switch_voltage,
};
static const struct of_device_id dw_mci_starfive_match[] = {
struct clk *clk_tx;
struct clk *clk_gtx;
struct clk *clk_gtxc;
+ struct clk *clk_rmii_rtx;
};
static void starfive_eth_fix_mac_speed(void *priv, unsigned int speed)
err = clk_set_rate(dwmac->clk_gtx, rate);
if (err < 0)
dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
+
+ err = clk_set_rate(dwmac->clk_rmii_rtx, rate);
+ if (err < 0)
+ dev_err(dwmac->dev, "failed to set rtx rate %lu\n", rate);
}
static const struct of_device_id starfive_eth_plat_match[] = {
goto disable_gtx;
}
+ dwmac->clk_rmii_rtx = devm_clk_get(&pdev->dev, "rmii_rtx");
+ if (IS_ERR(dwmac->clk_rmii_rtx)) {
+ err = PTR_ERR(dwmac->clk_rmii_rtx);
+ goto disable_gtx;
+ }
+
err = clk_prepare_enable(dwmac->clk_gtxc);
if (err < 0)
goto disable_gtx;
tristate "Motorcomm PHYs"
help
Enables support for Motorcomm network PHYs.
- Currently supports the YT8511 and YT8521 gigabit PHY.
+ Currently supports the YT8511/YT8521/YT8531 gigabit PHY.
config NATIONAL_PHY
tristate "National Semiconductor PHYs"
struct pinctrl *pinctrl;
struct pinctrl_state *perst_state_def;
struct pinctrl_state *perst_state_active;
- struct pinctrl_state *power_state_def;
- struct pinctrl_state *power_state_active;
};
static inline void plda_writel(struct plda_pcie *pcie, const u32 value,
return -EINVAL;
}
- pcie->power_state_def
- = pinctrl_lookup_state(pcie->pinctrl, "power-default");
- if (IS_ERR_OR_NULL(pcie->power_state_def)) {
- dev_err(dev, "Failed to get the power-default pinctrl handle\n");
- return -EINVAL;
- }
-
- pcie->power_state_active
- = pinctrl_lookup_state(pcie->pinctrl, "power-active");
- if (IS_ERR_OR_NULL(pcie->power_state_active)) {
- dev_err(dev, "Failed to get the power-active pinctrl handle\n");
- return -EINVAL;
- }
-
return 0;
}
int i, ret;
struct device *dev = &pcie->pdev->dev;
- if (pcie->power_state_active) {
- ret = pinctrl_select_state(pcie->pinctrl, pcie->power_state_active);
- if (ret)
- dev_err(dev, "Cannot set power pin to high\n");
- }
-
if (pcie->perst_state_active) {
ret = pinctrl_select_state(pcie->pinctrl, pcie->perst_state_active);
if (ret)
return ret;
release:
- if (pcie->power_state_def &&
- pinctrl_select_state(pcie->pinctrl, pcie->power_state_def))
- dev_err(dev, "Cannot set power pin to low\n");
plda_clk_rst_deinit(pcie);
pm_runtime_put_sync(&pdev->dev);
{25000000, 2400000000, 0x1, 0xC0, 0x000000, 0x0, 0x0D, 0x20, 0x16, 0x0A, 0x50, 0x15, 0x00, 0x18,},
{25000000, 2500000000, 0x1, 0xC8, 0x000000, 0x0, 0x0E, 0x21, 0x16, 0x0B, 0x53, 0x16, 0x00, 0x18,},
#elif (M31_DPHY_REFCLK == M31_DPHY_REFCLK_12M)
+ {12000000, 160000000, 0x0, 0x6a, 0xaa<<16|0xaa<<8|0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d,},
+ {12000000, 170000000, 0x0, 0x71, 0x55<<16|0x55<<8|0x55, 0x3, 0xb, 0x18, 0x11, 0x5, 0x2e, 0xd, 0x7, 0x3d,},
+ {12000000, 180000000, 0x0, 0x78, 0x0<<16|0x0<<8|0x0, 0x3, 0xb, 0x19, 0x12, 0x6, 0x30, 0xe, 0x7, 0x3e,},
+ {12000000, 190000000, 0x0, 0x7e, 0xaa<<16|0xaa<<8|0xaa, 0x3, 0xc, 0x1a, 0x12, 0x6, 0x33, 0xe, 0x7, 0x3e,},
+ {12000000, 200000000, 0x0, 0x85, 0x55<<16|0x55<<8|0x55, 0x3, 0xc, 0x1b, 0x13, 0x7, 0x35, 0xf, 0x7, 0x3f,},
+ {12000000, 320000000, 0x0, 0x6a, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0x8, 0x14, 0xf, 0x5, 0x2b, 0xd, 0x3, 0x23,},
+ {12000000, 330000000, 0x0, 0x6e, 0x0<<16|0x0<<8|0x0, 0x2, 0x8, 0x15, 0xf, 0x5, 0x2d, 0xd, 0x3, 0x23,},
+ {12000000, 340000000, 0x0, 0x71, 0x55<<16|0x55<<8|0x55, 0x2, 0x9, 0x15, 0xf, 0x5, 0x2e, 0xd, 0x3, 0x23,},
+ {12000000, 350000000, 0x0, 0x74, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0x9, 0x15, 0x10, 0x6, 0x2f, 0xe, 0x3, 0x24,},
+ {12000000, 360000000, 0x0, 0x78, 0x0<<16|0x0<<8|0x0, 0x2, 0x9, 0x16, 0x10, 0x6, 0x30, 0xe, 0x3, 0x24,},
+ {12000000, 370000000, 0x0, 0x7b, 0x55<<16|0x55<<8|0x55, 0x2, 0x9, 0x17, 0x10, 0x6, 0x32, 0xe, 0x3, 0x24,},
+ {12000000, 380000000, 0x0, 0x7e, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xa, 0x17, 0x10, 0x6, 0x33, 0xe, 0x3, 0x24,},
+ {12000000, 390000000, 0x0, 0x82, 0x0<<16|0x0<<8|0x0, 0x2, 0xa, 0x17, 0x11, 0x6, 0x35, 0xf, 0x3, 0x25,},
+ {12000000, 400000000, 0x0, 0x85, 0x55<<16|0x55<<8|0x55, 0x2, 0xa, 0x18, 0x11, 0x7, 0x35, 0xf, 0x3, 0x25,},
+ {12000000, 410000000, 0x0, 0x88, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xa, 0x19, 0x11, 0x7, 0x37, 0xf, 0x3, 0x25,},
+ {12000000, 420000000, 0x0, 0x8c, 0x0<<16|0x0<<8|0x0, 0x2, 0xa, 0x19, 0x12, 0x7, 0x38, 0x10, 0x3, 0x26,},
+ {12000000, 430000000, 0x0, 0x8f, 0x55<<16|0x55<<8|0x55, 0x2, 0xb, 0x19, 0x12, 0x7, 0x39, 0x10, 0x3, 0x26,},
+ {12000000, 440000000, 0x0, 0x92, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xb, 0x1a, 0x12, 0x7, 0x3b, 0x10, 0x3, 0x26,},
+ {12000000, 450000000, 0x0, 0x96, 0x0<<16|0x0<<8|0x0, 0x2, 0xb, 0x1b, 0x12, 0x8, 0x3c, 0x10, 0x3, 0x26,},
+ {12000000, 460000000, 0x0, 0x99, 0x55<<16|0x55<<8|0x55, 0x2, 0xb, 0x1b, 0x13, 0x8, 0x3d, 0x11, 0x3, 0x27,},
+ {12000000, 470000000, 0x0, 0x9c, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xc, 0x1b, 0x13, 0x8, 0x3e, 0x11, 0x3, 0x27,},
+ {12000000, 480000000, 0x0, 0xa0, 0x0<<16|0x0<<8|0x0, 0x2, 0xc, 0x1c, 0x13, 0x8, 0x40, 0x11, 0x3, 0x27,},
+ {12000000, 490000000, 0x0, 0xa3, 0x55<<16|0x55<<8|0x55, 0x2, 0xc, 0x1d, 0x14, 0x8, 0x42, 0x12, 0x3, 0x28,},
{12000000, 500000000, 0x0, 0xa6, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xc, 0x1d, 0x14, 0x9, 0x42, 0x12, 0x3, 0x28,},
{12000000, 510000000, 0x0, 0xaa, 0x0<<16|0x0<<8|0x0, 0x2, 0xc, 0x1e, 0x14, 0x9, 0x44, 0x12, 0x3, 0x28,},
{12000000, 520000000, 0x0, 0xad, 0x55<<16|0x55<<8|0x55, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x45, 0x13, 0x3, 0x29,},
return ret;
}
-/*
-*static int sf_dphy_remove(struct platform_device *pdev)
-*{
-* struct sf_dphy *dphy = dev_get_drvdata(&pdev->dev);
-* reset_control_assert(dphy->sys_rst);
-* //reset_control_assert(dphy->txbytehs_rst);
-* clk_disable_unprepare(dphy->txesc_clk);
-* return 0;
-*}
-*/
-
-#if 0
-static u32 top_sys_read32(struct sf_dphy *priv, u32 reg)
-{
- return ioread32(priv->topsys + reg);
-}
-
-
-static inline void top_sys_write32(struct sf_dphy *priv, u32 reg, u32 val)
-{
- iowrite32(val, priv->topsys + reg);
-}
-
-static void dsi_csi2tx_sel(struct sf_dphy *priv, int sel)
-{
- u32 temp = 0;
- temp = top_sys_read32(priv, SCFG_DSI_CSI_SEL);
- temp &= ~(0x1);
- temp |= (sel & 0x1);
- top_sys_write32(priv, SCFG_DSI_CSI_SEL, temp);
-}
-
-static void dphy_clane_hs_txready_sel(struct sf_dphy *priv, u32 ready_sel)
-{
- top_sys_write32(priv, SCFG_TXREADY_SRC_SEL_D, ready_sel);
- top_sys_write32(priv, SCFG_TXREADY_SRC_SEL_C, ready_sel);
- top_sys_write32(priv, SCFG_HS_PRE_ZERO_T_D, 0x30);
- top_sys_write32(priv, SCFG_HS_PRE_ZERO_T_C, 0x30);
-}
-
-static void mipi_tx_lxn_set(struct sf_dphy *priv, u32 reg, u32 n_hstx, u32 p_hstx)
-{
- u32 temp = 0;
-
- temp = n_hstx;
- temp |= p_hstx << 5;
- top_sys_write32(priv, reg, temp);
-}
-
-static void dphy_config(struct sf_dphy *priv, int bit_rate)
-{
- int pre_div, fbk_int, extd_cycle_sel;
- int dhs_pre_time, dhs_zero_time, dhs_trial_time;
- int chs_pre_time, chs_zero_time, chs_trial_time;
- int chs_clk_pre_time, chs_clk_post_time;
- u32 set_val = 0;
-
- mipi_tx_lxn_set(priv, SCFG_L0N_L0P_HSTX, 0x10, 0x10);
- mipi_tx_lxn_set(priv, SCFG_L1N_L1P_HSTX, 0x10, 0x10);
- mipi_tx_lxn_set(priv, SCFG_L2N_L2P_HSTX, 0x10, 0x10);
- mipi_tx_lxn_set(priv, SCFG_L3N_L3P_HSTX, 0x10, 0x10);
- mipi_tx_lxn_set(priv, SCFG_L4N_L4P_HSTX, 0x10, 0x10);
-
- if(bit_rate == 80) {
- pre_div=0x1, fbk_int=2*0x33, extd_cycle_sel=0x4,
- dhs_pre_time=0xe, dhs_zero_time=0x1d, dhs_trial_time=0x15,
- chs_pre_time=0x5, chs_zero_time=0x2b, chs_trial_time=0xd,
- chs_clk_pre_time=0xf,
- chs_clk_post_time=0x71;
- } else if (bit_rate == 100) {
- pre_div=0x1, fbk_int=2*0x40, extd_cycle_sel=0x4,
- dhs_pre_time=0x10, dhs_zero_time=0x21, dhs_trial_time=0x17,
- chs_pre_time=0x7, chs_zero_time=0x35, chs_trial_time=0xf,
- chs_clk_pre_time=0xf,
- chs_clk_post_time=0x73;
- } else if (bit_rate == 200) {
- pre_div=0x1, fbk_int=2*0x40, extd_cycle_sel=0x3;
- dhs_pre_time=0xc, dhs_zero_time=0x1b, dhs_trial_time=0x13;
- chs_pre_time=0x7, chs_zero_time=0x35, chs_trial_time=0xf,
- chs_clk_pre_time=0x7,
- chs_clk_post_time=0x3f;
- } else if(bit_rate == 300) {
- pre_div=0x1, fbk_int=2*0x60, extd_cycle_sel=0x3,
- dhs_pre_time=0x11, dhs_zero_time=0x25, dhs_trial_time=0x19,
- chs_pre_time=0xa, chs_zero_time=0x50, chs_trial_time=0x15,
- chs_clk_pre_time=0x7,
- chs_clk_post_time=0x45;
- } else if(bit_rate == 400) {
- pre_div=0x1, fbk_int=2*0x40, extd_cycle_sel=0x2,
- dhs_pre_time=0xa, dhs_zero_time=0x18, dhs_trial_time=0x11,
- chs_pre_time=0x7, chs_zero_time=0x35, chs_trial_time=0xf,
- chs_clk_pre_time=0x3,
- chs_clk_post_time=0x25;
- } else if(bit_rate == 500 ) {
- pre_div=0x1, fbk_int=2*0x50, extd_cycle_sel=0x2,
- dhs_pre_time=0xc, dhs_zero_time=0x1d, dhs_trial_time=0x14,
- chs_pre_time=0x9, chs_zero_time=0x42, chs_trial_time=0x12,
- chs_clk_pre_time=0x3,
- chs_clk_post_time=0x28;
- } else if(bit_rate == 600 ) {
- pre_div=0x1, fbk_int=2*0x60, extd_cycle_sel=0x2,
- dhs_pre_time=0xe, dhs_zero_time=0x23, dhs_trial_time=0x17,
- chs_pre_time=0xa, chs_zero_time=0x50, chs_trial_time=0x15,
- chs_clk_pre_time=0x3,
- chs_clk_post_time=0x2b;
- } else if(bit_rate == 700) {
- pre_div=0x1, fbk_int=2*0x38, extd_cycle_sel=0x1,
- dhs_pre_time=0x8, dhs_zero_time=0x14, dhs_trial_time=0xf,
- chs_pre_time=0x6, chs_zero_time=0x2f, chs_trial_time=0xe,
- chs_clk_pre_time=0x1,
- chs_clk_post_time=0x16;
- } else if(bit_rate == 800 ) {
- pre_div=0x1, fbk_int=2*0x40, extd_cycle_sel=0x1,
- dhs_pre_time=0x9, dhs_zero_time=0x17, dhs_trial_time=0x10,
- chs_pre_time=0x7, chs_zero_time=0x35, chs_trial_time=0xf,
- chs_clk_pre_time=0x1,
- chs_clk_post_time=0x18;
- } else if(bit_rate == 900 ) {
- pre_div=0x1, fbk_int=2*0x48, extd_cycle_sel=0x1,
- dhs_pre_time=0xa, dhs_zero_time=0x19, dhs_trial_time=0x12,
- chs_pre_time=0x8, chs_zero_time=0x3c, chs_trial_time=0x10,
- chs_clk_pre_time=0x1,
- chs_clk_post_time=0x19;
- } else if(bit_rate == 1000) {
- pre_div=0x1, fbk_int=2*0x50, extd_cycle_sel=0x1,
- dhs_pre_time=0xb, dhs_zero_time=0x1c, dhs_trial_time=0x13,
- chs_pre_time=0x9, chs_zero_time=0x42, chs_trial_time=0x12,
- chs_clk_pre_time=0x1,
- chs_clk_post_time=0x1b;
- } else if(bit_rate == 1100) {
- pre_div=0x1, fbk_int=2*0x58, extd_cycle_sel=0x1,
- dhs_pre_time=0xc, dhs_zero_time=0x1e, dhs_trial_time=0x15,
- chs_pre_time=0x9, chs_zero_time=0x4a, chs_trial_time=0x14,
- chs_clk_pre_time=0x1,
- chs_clk_post_time=0x1d;
- } else if(bit_rate == 1200) {
- pre_div=0x1, fbk_int=2*0x60, extd_cycle_sel=0x1,
- dhs_pre_time=0xe, dhs_zero_time=0x20, dhs_trial_time=0x16,
- chs_pre_time=0xa, chs_zero_time=0x50, chs_trial_time=0x15,
- chs_clk_pre_time=0x1,
- chs_clk_post_time=0x1e;
- } else if(bit_rate == 1300) {
- pre_div=0x1, fbk_int=2*0x34, extd_cycle_sel=0x0,
- dhs_pre_time=0x7, dhs_zero_time=0x12, dhs_trial_time=0xd,
- chs_pre_time=0x5, chs_zero_time=0x2c, chs_trial_time=0xd,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0xf;
- } else if(bit_rate == 1400) {
- pre_div=0x1, fbk_int=2*0x38, extd_cycle_sel=0x0,
- dhs_pre_time=0x7, dhs_zero_time=0x14, dhs_trial_time=0xe,
- chs_pre_time=0x6, chs_zero_time=0x2f, chs_trial_time=0xe,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x10;
- } else if(bit_rate == 1500) {
- pre_div=0x1, fbk_int=2*0x3c, extd_cycle_sel=0x0,
- dhs_pre_time=0x8, dhs_zero_time=0x14, dhs_trial_time=0xf,
- chs_pre_time=0x6, chs_zero_time=0x32, chs_trial_time=0xe,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x11;
- } else if(bit_rate == 1600) {
- pre_div=0x1, fbk_int=2*0x40, extd_cycle_sel=0x0,
- dhs_pre_time=0x9, dhs_zero_time=0x15, dhs_trial_time=0x10,
- chs_pre_time=0x7, chs_zero_time=0x35, chs_trial_time=0xf,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x12;
- } else if(bit_rate == 1700) {
- pre_div=0x1, fbk_int=2*0x44, extd_cycle_sel=0x0,
- dhs_pre_time=0x9, dhs_zero_time=0x17, dhs_trial_time=0x10,
- chs_pre_time=0x7, chs_zero_time=0x39, chs_trial_time=0x10,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x12;
- } else if(bit_rate == 1800) {
- pre_div=0x1, fbk_int=2*0x48, extd_cycle_sel=0x0,
- dhs_pre_time=0xa, dhs_zero_time=0x18, dhs_trial_time=0x11,
- chs_pre_time=0x8, chs_zero_time=0x3c, chs_trial_time=0x10,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x13;
- } else if(bit_rate == 1900) {
- pre_div=0x1, fbk_int=2*0x4c, extd_cycle_sel=0x0,
- dhs_pre_time=0xa, dhs_zero_time=0x1a, dhs_trial_time=0x12,
- chs_pre_time=0x8, chs_zero_time=0x3f, chs_trial_time=0x11,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x14;
- } else if(bit_rate == 2000) {
- pre_div=0x1, fbk_int=2*0x50, extd_cycle_sel=0x0,
- dhs_pre_time=0xb, dhs_zero_time=0x1b, dhs_trial_time=0x13,
- chs_pre_time=0x9, chs_zero_time=0x42, chs_trial_time=0x12,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x15;
- } else if(bit_rate == 2100) {
- pre_div=0x1, fbk_int=2*0x54, extd_cycle_sel=0x0,
- dhs_pre_time=0xb, dhs_zero_time=0x1c, dhs_trial_time=0x13,
- chs_pre_time=0x9, chs_zero_time=0x46, chs_trial_time=0x13,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x15;
- } else if(bit_rate == 2200) {
- pre_div=0x1, fbk_int=2*0x5b, extd_cycle_sel=0x0,
- dhs_pre_time=0xc, dhs_zero_time=0x1d, dhs_trial_time=0x14,
- chs_pre_time=0x9, chs_zero_time=0x4a, chs_trial_time=0x14,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x16;
- } else if(bit_rate == 2300) {
- pre_div=0x1, fbk_int=2*0x5c, extd_cycle_sel=0x0,
- dhs_pre_time=0xc, dhs_zero_time=0x1f, dhs_trial_time=0x15,
- chs_pre_time=0xa, chs_zero_time=0x4c, chs_trial_time=0x14,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x17;
- } else if(bit_rate == 2400) {
- pre_div=0x1, fbk_int=2*0x60, extd_cycle_sel=0x0,
- dhs_pre_time=0xd, dhs_zero_time=0x20, dhs_trial_time=0x16,
- chs_pre_time=0xa, chs_zero_time=0x50, chs_trial_time=0x15,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x18;
- } else if(bit_rate == 2500) {
- pre_div=0x1, fbk_int=2*0x64, extd_cycle_sel=0x0,
- dhs_pre_time=0xe, dhs_zero_time=0x21, dhs_trial_time=0x16,
- chs_pre_time=0xb, chs_zero_time=0x53, chs_trial_time=0x16,
- chs_clk_pre_time=0x0,
- chs_clk_post_time=0x18;
- } else {
- //default bit_rate == 700
- pre_div=0x1, fbk_int=2*0x38, extd_cycle_sel=0x1,
- dhs_pre_time=0x8, dhs_zero_time=0x14, dhs_trial_time=0xf,
- chs_pre_time=0x6, chs_zero_time=0x2f, chs_trial_time=0xe,
- chs_clk_pre_time=0x1,
- chs_clk_post_time=0x16;
- }
- top_sys_write32(priv, SCFG_REFCLK_SEL, 0x3);
-
- set_val = 0
- | (1 << OFFSET_CFG_L1_SWAP_SEL)
- | (4 << OFFSET_CFG_L2_SWAP_SEL)
- | (2 << OFFSET_CFG_L3_SWAP_SEL)
- | (3 << OFFSET_CFG_L4_SWAP_SEL);
- top_sys_write32(priv, SCFG_LX_SWAP_SEL, set_val);
-
- set_val = 0
- | (0 << OFFSET_SCFG_PWRON_READY_N)
- | (1 << OFFSET_RG_CDTX_PLL_FM_EN)
- | (0 << OFFSET_SCFG_PLLSSC_EN)
- | (1 << OFFSET_RG_CDTX_PLL_LDO_STB_X2_EN);
- top_sys_write32(priv, SCFG_DBUS_PW_PLL_SSC_LD0, set_val);
-
- set_val = fbk_int
- | (pre_div << 9);
- top_sys_write32(priv, SCFG_RG_CDTX_PLL_FBK_PRE, set_val);
-
- top_sys_write32(priv, SCFG_RG_EXTD_CYCLE_SEL, extd_cycle_sel);
-
- set_val = chs_zero_time
- | (dhs_pre_time << OFFSET_DHS_PRE_TIME)
- | (dhs_trial_time << OFFSET_DHS_TRIAL_TIME)
- | (dhs_zero_time << OFFSET_DHS_ZERO_TIME);
- top_sys_write32(priv, SCFG_RG_CLANE_DLANE_TIME, set_val);
-
- set_val = chs_clk_post_time
- | (chs_clk_pre_time << OFFSET_CHS_PRE_TIME)
- | (chs_pre_time << OFFSET_CHS_TRIAL_TIME)
- | (chs_trial_time << OFFSET_CHS_ZERO_TIME);
- top_sys_write32(priv, SCFG_RG_CLANE_HS_TIME, set_val);
-
-}
-
-static void reset_dphy(struct sf_dphy *priv, int resetb)
-{
- u32 cfg_dsc_enable = 0x01;//bit0
-
- u32 precfg = top_sys_read32(priv, SCFG_PHY_RESETB);
- precfg &= ~(cfg_dsc_enable);
- precfg |= (resetb&cfg_dsc_enable);
- top_sys_write32(priv, SCFG_PHY_RESETB, precfg);
-}
-
-static void polling_dphy_lock(struct sf_dphy *priv)
-{
- int pll_unlock;
-
- udelay(10);
-
- do {
- pll_unlock = top_sys_read32(priv, SCFG_GRS_CDTX_PLL) >> 3;
- pll_unlock &= 0x1;
- } while(pll_unlock == 0x1);
-}
-
-static int sf_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
-{ //dev_info(dphy->dev,"--->sf_dphy_configure\n");
- struct sf_dphy *dphy = phy_get_drvdata(phy);
- uint32_t bit_rate = 800000000/1000000UL;//new mipi panel clock setting
- //uint32_t bit_rate = 500000000/1000000UL;//7110 mipi panel clock setting
-
-
- dphy_config(dphy, bit_rate);
- reset_dphy(dphy, 1);
- mdelay(10);
- polling_dphy_lock(dphy);
-
- //dev_info(dphy->dev,"--->sf_dphy_configure\n");
- return 0;
-}
-#endif
-
static int is_pll_locked(struct sf_dphy *dphy)
{
int tmp = sf_dphy_get_reg(dphy->topsys + 0x8,
const uint32_t AON_POWER_READY_N_active = 0;
dphy = phy_get_drvdata(phy);
//bitrate = 680000000;//1228M 60fps
- bitrate = 750000000;//1188M 60fps
+ //bitrate = 750000000;//1188M 60fps
+ // bitrate = 490000000;//1188M 60fps
+ bitrate = opts->mipi_dphy.hs_clk_rate;//1188M 60fps
+ printk("sys_m31_dphy_tx_configure opts->mipi_dphy.hs_clk_rate = %ld\n",opts->mipi_dphy.hs_clk_rate);
+
sf_dphy_set_reg(dphy->topsys + 0x8, 0x10,
RG_CDTX_L0N_HSTX_RES_SHIFT, RG_CDTX_L0N_HSTX_RES_MASK);
CFG_L0_SWAP_SEL_SHIFT, CFG_L0_SWAP_SEL_MASK);//Lane setting
sf_dphy_set_reg(dphy->topsys, 0x1,
CFG_L1_SWAP_SEL_SHIFT, CFG_L1_SWAP_SEL_MASK);
- sf_dphy_set_reg(dphy->topsys, 0x4,
- CFG_L2_SWAP_SEL_SHIFT, CFG_L2_SWAP_SEL_MASK);
sf_dphy_set_reg(dphy->topsys, 0x2,
- CFG_L3_SWAP_SEL_SHIFT, CFG_L3_SWAP_SEL_MASK);
+ CFG_L2_SWAP_SEL_SHIFT, CFG_L2_SWAP_SEL_MASK);
sf_dphy_set_reg(dphy->topsys, 0x3,
+ CFG_L3_SWAP_SEL_SHIFT, CFG_L3_SWAP_SEL_MASK);
+ sf_dphy_set_reg(dphy->topsys, 0x4,
CFG_L4_SWAP_SEL_SHIFT, CFG_L4_SWAP_SEL_MASK);
//PLL setting
sf_dphy_set_reg(dphy->topsys + 0x1c, 0x0,
static int sf_dphy_init(struct phy *phy)
{
+ struct sf_dphy *dphy = phy_get_drvdata(phy);
+ uint32_t temp;
+ int ret;
+
+ temp = 0;
+ temp = sf_dphy_get_reg(dphy->aonsys, AON_GP_REG_SHIFT,AON_GP_REG_MASK);
+ dev_info(dphy->dev, "GET_AON_GP_REG\n");
+
+ if (!(temp & DPHY_TX_PSW_EN_MASK)) {
+ temp |= DPHY_TX_PSW_EN_MASK;
+ sf_dphy_set_reg(dphy->aonsys, temp,AON_GP_REG_SHIFT,AON_GP_REG_MASK);
+ }
+ dev_info(dphy->dev, "control ECO\n");
+
+ //pmic turn on
+ ret = regulator_enable(dphy->mipitx_0p9);
+ if (ret) {
+ dev_err(dphy->dev, "Cannot enable mipitx_0p9 regulator\n");
+ //goto err_reg_0p9;
+ }
+ udelay(100);
+ ret = regulator_enable(dphy->mipitx_1p8);
+ if (ret) {
+ dev_err(dphy->dev, "Cannot enable mipitx_1p8 regulator\n");
+ //goto err_reg_1p8;
+ }
+ udelay(100);
+ //mipi_pmic setting
+
return 0;
}
struct sf_dphy *dphy;
struct resource *res;
int ret;
- uint32_t temp;
dev_info(&pdev->dev, "sf_dphy_probe begin\n");
dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
// this power switch control bit was added in ECO, check ECO item "aon psw_en" for detail
dev_info(dphy->dev, "control ECO\n");
dphy->aonsys = ioremap(0x17010000, 0x10000);
- temp = 0;
- temp = sf_dphy_get_reg(dphy->aonsys, AON_GP_REG_SHIFT,AON_GP_REG_MASK);
- dev_info(dphy->dev, "GET_AON_GP_REG\n");
-
- if (!(temp & DPHY_TX_PSW_EN_MASK)) {
- temp |= DPHY_TX_PSW_EN_MASK;
- sf_dphy_set_reg(dphy->aonsys, temp,AON_GP_REG_SHIFT,AON_GP_REG_MASK);
- }
- dev_info(dphy->dev, "control ECO\n");
//mipi_pmic setting
- dphy->mipitx_1p8 = devm_regulator_get(&pdev->dev, "mipitx_1p8");
+ dphy->mipitx_1p8 = devm_regulator_get(&pdev->dev, "mipi_1p8");
if (IS_ERR(dphy->mipitx_1p8))
return PTR_ERR(dphy->mipitx_1p8);
- dphy->mipitx_0p9 = devm_regulator_get(&pdev->dev, "mipitx_0p9");
+ dphy->mipitx_0p9 = devm_regulator_get(&pdev->dev, "mipi_0p9");
if (IS_ERR(dphy->mipitx_0p9))
return PTR_ERR(dphy->mipitx_0p9);
- //pmic turn on
- ret = regulator_enable(dphy->mipitx_0p9);
- if (ret) {
- dev_err(&pdev->dev, "Cannot enable mipitx_0p9 regulator\n");
- //goto err_reg_0p9;
- }
- udelay(100);
- ret = regulator_enable(dphy->mipitx_1p8);
- if (ret) {
- dev_err(&pdev->dev, "Cannot enable mipitx_1p8 regulator\n");
- //goto err_reg_1p8;
- }
- udelay(100);
- //mipi_pmic setting
ret = sf_dphy_clkrst_get(&pdev->dev, dphy);
AXP15060_VOL_CTRL_ALDO_3, AXP15060_ALDO3_V_OUT_MASK,
AXP15060_ON_OFF_CTRL_2, AXP15060_PWR_OUT_ALDO3_MASK),
- AXP15060_DESC(ALDO4, "sdio_vdd", 700, 3300, 100,
- AXP15060_VOL_CTRL_ALDO_4, AXP15060_ALDO4_V_OUT_MASK,
- AXP15060_ON_OFF_CTRL_2, AXP15060_PWR_OUT_ALDO4_MASK),
-
AXP15060_DESC(ALDO5, "hdmi_0p9", 700, 3300, 100,
AXP15060_VOL_CTRL_ALDO_5, AXP15060_ALDO5_V_OUT_MASK,
AXP15060_ON_OFF_CTRL_2, AXP15060_PWR_OUT_ALDO5_MASK),
static struct of_regulator_match axp15060_matches[] = {
{ .name = "mipi_0p9", },
{ .name = "hdmi_1p8", },
- { .name = "sdio_vdd", },
{ .name = "hdmi_0p9", },
{ .name = "cpu_vdd", },
};
enum axp15060_reg_id {
AXP15060_ID_ALDO1 = 0,
AXP15060_ID_ALDO3,
- AXP15060_ID_ALDO4,
AXP15060_ID_ALDO5,
AXP15060_ID_DCDC2,
AXP15060_MAX_REGULATORS,
projects / platform / kernel / linux-starfive.git / commitdiff