ARM: OMAP3: clock: use clk_features flags for omap3 DPLL4 checks
authorTero Kristo <t-kristo@ti.com>
Fri, 3 Oct 2014 13:57:10 +0000 (16:57 +0300)
committerPaul Walmsley <paul@pwsan.com>
Thu, 13 Nov 2014 16:25:06 +0000 (09:25 -0700)
DPLL4 can't be reprogrammed on OMAP3430 ES1.0 due to hardware limitation.
Currently, the code does runtime omap_rev() check to see the chip it is
being executed on, instead, change this to use clk_features flags.
This avoids need for runtime omap_rev() checks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
arch/arm/mach-omap2/clock.c
arch/arm/mach-omap2/clock.h
arch/arm/mach-omap2/clock3xxx.c

index 500530d..c2b2398 100644 (file)
@@ -771,4 +771,8 @@ void __init ti_clk_init_features(void)
                ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
        else if (cpu_is_omap34xx())
                ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
+
+       /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
+       if (omap_rev() == OMAP3430_REV_ES1_0)
+               ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
 }
index 4592a27..641337c 100644 (file)
@@ -234,6 +234,7 @@ struct ti_clk_features {
 };
 
 #define TI_CLK_DPLL_HAS_FREQSEL                (1 << 0)
+#define TI_CLK_DPLL4_DENY_REPROGRAM    (1 << 1)
 
 extern struct ti_clk_features ti_clk_features;
 
index 0b02b41..9a25601 100644 (file)
@@ -46,7 +46,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
         * on 3430ES1 prevents us from changing DPLL multipliers or dividers
         * on DPLL4.
         */
-       if (omap_rev() == OMAP3430_REV_ES1_0) {
+       if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
                pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
                return -EINVAL;
        }