const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isImm()) {
+ O << markup("<imm:");
if (PrintBranchImmAsAddress) {
uint64_t Target = Address + Op.getImm();
if (MAI.getCodePointerSize() == 4)
O << formatHex(Target);
} else
O << formatImm(Op.getImm());
+ O << markup(">");
} else {
assert(Op.isExpr() && "unknown pcrel immediate operand");
// If a symbolic branch target was added as a constant expression then print
const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
int64_t Address;
if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
- O << formatHex((uint64_t)Address);
+ O << markup("<imm:") << formatHex((uint64_t)Address) << markup(">");
} else {
// Otherwise, just print the expression.
Op.getExpr()->print(O, &MAI);
#include "X86GenAsmWriter1.inc"
void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
- OS << getRegisterName(RegNo);
+ OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
}
void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
if (Op.isReg()) {
printRegName(O, Op.getReg());
} else if (Op.isImm()) {
- O << formatImm((int64_t)Op.getImm());
+ O << markup("<imm:") << formatImm((int64_t)Op.getImm()) << markup(">");
} else {
assert(Op.isExpr() && "unknown operand kind in printOperand");
O << "offset ";
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
- O << '[';
+ O << markup("<mem:") << '[';
bool NeedPlus = false;
if (BaseReg.getReg()) {
DispVal = -DispVal;
}
}
- O << formatImm(DispVal);
+ O << markup("<imm:") << formatImm(DispVal) << markup(">");
}
}
- O << ']';
+ O << ']' << markup(">");
}
void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
raw_ostream &O) {
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + 1, O);
- O << '[';
+ O << markup("<mem:") << '[';
printOperand(MI, Op, O);
- O << ']';
+ O << ']' << markup(">");
}
void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
raw_ostream &O) {
// DI accesses are always ES-based.
- O << "es:[";
+ O << "es:" << markup("<mem:") << '[';
printOperand(MI, Op, O);
- O << ']';
+ O << ']' << markup(">");
}
void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + 1, O);
- O << '[';
+ O << markup("<mem:") << '[';
if (DispSpec.isImm()) {
- O << formatImm(DispSpec.getImm());
+ O << markup("<imm:") << formatImm(DispSpec.getImm()) << markup(">");
} else {
assert(DispSpec.isExpr() && "non-immediate displacement?");
DispSpec.getExpr()->print(O, &MAI);
}
- O << ']';
+ O << ']' << markup(">");
}
void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
if (MI->getOperand(Op).isExpr())
return MI->getOperand(Op).getExpr()->print(O, &MAI);
- O << formatImm(MI->getOperand(Op).getImm() & 0xff);
+ O << markup("<imm:") << formatImm(MI->getOperand(Op).getImm() & 0xff)
+ << markup(">");
}
void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,