u8 res5[0x19fc - 0xa00];
};
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLY__ */
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
u32 dayr;
u32 dayalarm;
};
-#endif /* __ASSEMBLY__*/
+#endif /* __ASSEMBLY__ */
#endif /* __MX28_REGS_RTC_H__ */
u32 cnr;
};
-#endif /* __ASSEMBLER__*/
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
*/
#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
-#endif /* __ASSEMBLER__*/
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
u32 reserved_3[3];
};
-#endif /* __ASSEMBLER__*/
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */
u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */
};
-#endif /* __ASSEMBLER__ */
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_IMX_REGS_H__ */
u32 cpxcfg3;
};
-#endif /* __ASSEMBLER__*/
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_IMX_REGS_H__ */
phys_addr_t socfpga_get_clkmgr_addr(void);
-#ifndef __ASSEMBLER__
+#ifndef __ASSEMBLY__
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
#ifndef CLOCK_MANAGER_ARRIA10
#define CLOCK_MANAGER_ARRIA10
-#ifndef __ASSEMBLER__
+#ifndef __ASSEMBLY__
/* Clock manager group */
#define CLKMGR_A10_CTRL 0x00
unsigned int cm_get_qspi_controller_clk_hz(void);
-#endif /* __ASSEMBLER__ */
+#endif /* __ASSEMBLY__ */
#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
#ifndef _CLOCK_MANAGER_GEN5_H_
#define _CLOCK_MANAGER_GEN5_H_
-#ifndef __ASSEMBLER__
+#ifndef __ASSEMBLY__
struct cm_config {
/* main group */
/* Clock configuration accessors */
int cm_basic_init(const struct cm_config * const cfg);
const struct cm_config * const cm_get_default_config(void);
-#endif /* __ASSEMBLER__ */
+#endif /* __ASSEMBLY__ */
#define LOCKED_MASK \
(CLKMGR_INTER_SDRPLLLOCKED_MASK | \
u32 niosreserve2;
};
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLY__ */
#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT 24
#define BSEC_OTP_MAC 57
#define BSEC_OTP_BOARD 59
-#endif /* __ASSEMBLY__*/
+#endif /* __ASSEMBLY__ */
#endif /* _MACH_STM32_H_ */
#define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t)
-#if !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLY__)
/**
* Information about the previous MTRR state, set up by mtrr_open()
#define AP_DEFAULT_BASE 0x30000
#define AP_DEFAULT_SIZE 0x10000
-#ifndef __ASSEMBLER__
+#ifndef __ASSEMBLY__
/**
* struct sipi_params_16bit - 16-bit SIPI entry-point parameters
extern char sipi_params_16bit[];
extern char sipi_params[];
-#endif /* __ASSEMBLER__ */
+#endif /* __ASSEMBLY__ */
#endif
struct entry_point_info bl31_ep_info;
};
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLY__ */
#endif /* __BL_COMMON_H__ */
#ifndef _ELF_H
#define _ELF_H
-#ifndef __ASSEMBLER__
+#ifndef __ASSEMBLY__
#include "compiler.h"
/* This version doesn't work for 64-bit ABIs - Erik */
#define R_RISCV_64 2
#define R_RISCV_RELATIVE 3
-#ifndef __ASSEMBLER__
+#ifndef __ASSEMBLY__
int valid_elf_image(unsigned long addr);
unsigned long load_elf64_image_phdr(unsigned long addr);
unsigned long load_elf64_image_shdr(unsigned long addr);