riscv: drop some idefs from CMO initialization

Wrapping things in #ifdefs makes the code harder to read
while we also have IS_ENABLED() macros to do this in regular code
and the extension detection is not _that_ runtime critical.

So define a stub for riscv_noncoherent_supported() in the
non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
us IS_ENABLED.

Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20220905111027.2463297-3-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index 202c83f677b2ede1bc0992fffb91442930ffa74b..bffa711aaf647fc43463a85f7f617cf2058b3bc8 100644 (file)
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
 static bool errata_probe_cmo(unsigned int stage,
                             unsigned long arch_id, unsigned long impid)
 {
-#ifdef CONFIG_ERRATA_THEAD_CMO
+       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
+               return false;
+
        if (arch_id != 0 || impid != 0)
                return false;
 
@@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
 
        riscv_noncoherent_supported();
        return true;
-#else
-       return false;
-#endif
 }
 
 static u32 thead_errata_probe(unsigned int stage,

diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index a60acaecfedab6ad09e578b1f1a98b04a08541c7..4363d0beb38a15e5f0ba806611f736ad8dc90f5a 100644 (file)
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
 
 #ifdef CONFIG_RISCV_DMA_NONCOHERENT
 void riscv_noncoherent_supported(void);
+#else
+static inline void riscv_noncoherent_supported(void) {}
 #endif
 
 /*

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 764ea220161f65982cf2f62d6949c03102a703b7..729f7a218093acea8bcc973ae0c9ea1d02685894 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
 
 static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
 {
-#ifdef CONFIG_RISCV_ISA_ZICBOM
-       switch (stage) {
-       case RISCV_ALTERNATIVES_EARLY_BOOT:
+       if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
+               return false;
+
+       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+               return false;
+
+       if (!riscv_isa_extension_available(NULL, ZICBOM))
                return false;
-       default:
-               if (riscv_isa_extension_available(NULL, ZICBOM)) {
-                       riscv_noncoherent_supported();
-                       return true;
-               } else {
-                       return false;
-               }
-       }
-#endif
 
-       return false;
+       riscv_noncoherent_supported();
+       return true;
 }
 
 /*