arm: dts: ls1028a: move the FlexSPI controller node
authorMichael Walle <michael@walle.cc>
Wed, 13 Oct 2021 16:14:06 +0000 (18:14 +0200)
committerPriyanka Jain <priyanka.jain@nxp.com>
Tue, 9 Nov 2021 11:48:23 +0000 (17:18 +0530)
While inserting it into the new location, keep it sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/dts/fsl-ls1028a.dtsi

index de85fdd..6d80b32 100644 (file)
                                          IRQ_TYPE_LEVEL_LOW)>;
        };
 
-       fspi: flexspi@20c0000 {
-               compatible = "nxp,lx2160a-fspi";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               reg = <0x0 0x20c0000 0x0 0x10000>,
-                     <0x0 0x20000000 0x0 0x10000000>;
-               reg-names = "fspi_base", "fspi_mmap";
-               clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-               clock-names = "fspi_en", "fspi";
-               interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-               status = "disabled";
-       };
-
        serial0: serial@21c0500 {
                device_type = "serial";
                compatible = "fsl,ns16550", "ns16550a";
                        clocks = <&clockgen 4 0>;
                        status = "disabled";
                };
+
+               fspi: flexspi@20c0000 {
+                       compatible = "nxp,lx2160a-fspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x20c0000 0x0 0x10000>,
+                             <0x0 0x20000000 0x0 0x10000000>;
+                       reg-names = "fspi_base", "fspi_mmap";
+                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clock-names = "fspi_en", "fspi";
+                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
        };
 };