net: dwc_eth_qos: Revert some changes of commit 3a97da12ee7b

Revert some changes of commit 3a97da12ee7b ("net: dwc_eth_qos: add dwc
eqos for imx support") that were probably added by mistake.

One of these changes can lead to received data corruption (enabling
FUP and FEP bits). Another causes invalid register rxq_ctrl0 settings
for some platforms. And another makes some writes at unknown memory
location.

Fixes: 3a97da12ee7b ("net: dwc_eth_qos: add dwc eqos for imx support")
Signed-off-by: Daniil Stas <daniil.stas@posteo.net>
Cc: Ye Li <ye.li@nxp.com>
Cc: Fugang Duan <fugang.duan@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 2f088c7..b012bed 100644 (file)
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -172,8 +172,6 @@ struct eqos_mtl_regs {
 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK          0x3f
 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC              BIT(7)
 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF               BIT(5)
-#define EQOS_MTL_RXQ0_OPERATION_MODE_FEP               BIT(4)
-#define EQOS_MTL_RXQ0_OPERATION_MODE_FUP               BIT(3)
 
 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT                 16
 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK                  0x7fff
@@ -1222,7 +1220,6 @@ static int eqos_start(struct udevice *dev)
        }
 
        /* Configure MTL */
-       writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
 
        /* Enable Store and Forward mode for TX */
        /* Program Tx operating mode */
@@ -1236,9 +1233,7 @@ static int eqos_start(struct udevice *dev)
 
        /* Enable Store and Forward mode for RX, since no jumbo frame */
        setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
-                    EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
-                    EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
-                    EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
+                    EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
 
        /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
        val = readl(&eqos->mac_regs->hw_feature1);
@@ -1314,12 +1309,6 @@ static int eqos_start(struct udevice *dev)
                        eqos->config->config_mac <<
                        EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
 
-       clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
-                       EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
-                       EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
-                       0x2 <<
-                       EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
-
        /* Multicast and Broadcast Queue Enable */
        setbits_le32(&eqos->mac_regs->unused_0a4,
                     0x00100000);