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perf/x86/intel/uncore: Fix Intel SPR M2PCIE event constraints
author
Kan Liang
<kan.liang@linux.intel.com>
Thu, 26 Aug 2021 15:32:42 +0000
(08:32 -0700)
committer
Peter Zijlstra
<peterz@infradead.org>
Tue, 31 Aug 2021 11:59:37 +0000
(13:59 +0200)
Similar to the ICX M2PCIE events, some of the SPR M2PCIE events also
have constraints. Add the constraints for SPR M2PCIE.
Fixes: f85ef898f884 ("perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link:
https://lkml.kernel.org/r/1629991963-102621-7-git-send-email-kan.liang@linux.intel.com
arch/x86/events/intel/uncore_snbep.c
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diff --git
a/arch/x86/events/intel/uncore_snbep.c
b/arch/x86/events/intel/uncore_snbep.c
index 2d75d212c8cc43b00dd0b22b169ae99757475252..cd53057fd52de628799ad26139cfdedc549fc536 100644
(file)
--- a/
arch/x86/events/intel/uncore_snbep.c
+++ b/
arch/x86/events/intel/uncore_snbep.c
@@
-5690,9
+5690,16
@@
static struct intel_uncore_type spr_uncore_irp = {
};
+static struct event_constraint spr_uncore_m2pcie_constraints[] = {
+ UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
+ EVENT_CONSTRAINT_END
+};
+
static struct intel_uncore_type spr_uncore_m2pcie = {
SPR_UNCORE_COMMON_FORMAT(),
.name = "m2pcie",
+ .constraints = spr_uncore_m2pcie_constraints,
};
static struct intel_uncore_type spr_uncore_pcu = {