memory: tegra: Print out info-level once per driver probe
authorDmitry Osipenko <digetx@gmail.com>
Tue, 30 Mar 2021 23:04:45 +0000 (02:04 +0300)
committerKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Thu, 1 Apr 2021 17:58:22 +0000 (19:58 +0200)
Probing of EMC drivers may be deferred and in this case we get duplicated
info messages during kernel boot. Use dev_info_once() helper to silence
the duplicated messages.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20210330230445.26619-7-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
drivers/memory/tegra/tegra124-emc.c
drivers/memory/tegra/tegra20-emc.c
drivers/memory/tegra/tegra30-emc.c

index 874e1a0..5699d90 100644 (file)
@@ -905,7 +905,7 @@ static int emc_init(struct tegra_emc *emc)
        else
                emc->dram_bus_width = 32;
 
-       dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
+       dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
 
        emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
        emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
@@ -1419,8 +1419,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
                goto put_hw_table;
        }
 
-       dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
-                hw_version, clk_get_rate(emc->clk) / 1000000);
+       dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
+                     hw_version, clk_get_rate(emc->clk) / 1000000);
 
        /* first dummy rate-set initializes voltage state */
        err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
@@ -1475,9 +1475,9 @@ static int tegra_emc_probe(struct platform_device *pdev)
                if (err)
                        return err;
        } else {
-               dev_info(&pdev->dev,
-                        "no memory timings for RAM code %u found in DT\n",
-                        ram_code);
+               dev_info_once(&pdev->dev,
+                             "no memory timings for RAM code %u found in DT\n",
+                             ram_code);
        }
 
        err = emc_init(emc);
index d653a6b..da8a0da 100644 (file)
@@ -411,12 +411,12 @@ static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
        sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
             NULL);
 
-       dev_info(emc->dev,
-                "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
-                emc->num_timings,
-                tegra_read_ram_code(),
-                emc->timings[0].rate / 1000000,
-                emc->timings[emc->num_timings - 1].rate / 1000000);
+       dev_info_once(emc->dev,
+                     "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
+                     emc->num_timings,
+                     tegra_read_ram_code(),
+                     emc->timings[0].rate / 1000000,
+                     emc->timings[emc->num_timings - 1].rate / 1000000);
 
        return 0;
 }
@@ -429,7 +429,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev)
        int err;
 
        if (of_get_child_count(dev->of_node) == 0) {
-               dev_info(dev, "device-tree doesn't have memory timings\n");
+               dev_info_once(dev, "device-tree doesn't have memory timings\n");
                return NULL;
        }
 
@@ -496,7 +496,7 @@ static int emc_setup_hw(struct tegra_emc *emc)
        else
                emc->dram_bus_width = 32;
 
-       dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
+       dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
 
        return 0;
 }
@@ -931,8 +931,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
                goto put_hw_table;
        }
 
-       dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
-                hw_version, clk_get_rate(emc->clk) / 1000000);
+       dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
+                     hw_version, clk_get_rate(emc->clk) / 1000000);
 
        /* first dummy rate-set initializes voltage state */
        err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
index 6985da0..829f6d6 100644 (file)
@@ -998,12 +998,12 @@ static int emc_load_timings_from_dt(struct tegra_emc *emc,
        if (err)
                return err;
 
-       dev_info(emc->dev,
-                "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
-                emc->num_timings,
-                tegra_read_ram_code(),
-                emc->timings[0].rate / 1000000,
-                emc->timings[emc->num_timings - 1].rate / 1000000);
+       dev_info_once(emc->dev,
+                     "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
+                     emc->num_timings,
+                     tegra_read_ram_code(),
+                     emc->timings[0].rate / 1000000,
+                     emc->timings[emc->num_timings - 1].rate / 1000000);
 
        return 0;
 }
@@ -1015,7 +1015,7 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev)
        int err;
 
        if (of_get_child_count(dev->of_node) == 0) {
-               dev_info(dev, "device-tree doesn't have memory timings\n");
+               dev_info_once(dev, "device-tree doesn't have memory timings\n");
                return NULL;
        }
 
@@ -1503,8 +1503,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
                goto put_hw_table;
        }
 
-       dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
-                hw_version, clk_get_rate(emc->clk) / 1000000);
+       dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
+                     hw_version, clk_get_rate(emc->clk) / 1000000);
 
        /* first dummy rate-set initializes voltage state */
        err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));