RISC-V: add single letter extensions to riscv_isa_ext

So that riscv_fill_hwcap() can use riscv_isa_ext to probe for single
letter extensions, add them to it.
As a result, what gets spat out in /proc/cpuinfo will become borked, as
single letter extensions will be printed as part of the base extensions
and while printing from riscv_isa_arr. Take the opportunity to unify the
printing of the isa string, using the new member of riscv_isa_ext_data
in the process.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230713-despite-bright-de00ac888cc7@wendy
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index aa17eeb..4f1f12f 100644 (file)
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -164,41 +164,26 @@ arch_initcall(riscv_cpuinfo_init);
 
 #ifdef CONFIG_PROC_FS
 
-static void print_isa_ext(struct seq_file *f)
-{
-       for (int i = 0; i < riscv_isa_ext_count; i++) {
-               const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i];
-               if (!__riscv_isa_extension_available(NULL, edata->id))
-                       continue;
-
-               seq_printf(f, "_%s", edata->name);
-       }
-}
-
-/*
- * These are the only valid base (single letter) ISA extensions as per the spec.
- * It also specifies the canonical order in which it appears in the spec.
- * Some of the extension may just be a place holder for now (B, K, P, J).
- * This should be updated once corresponding extensions are ratified.
- */
-static const char base_riscv_exts[13] = "imafdqcbkjpvh";
-
 static void print_isa(struct seq_file *f)
 {
-       int i;
-
        seq_puts(f, "isa\t\t: ");
+
        if (IS_ENABLED(CONFIG_32BIT))
                seq_write(f, "rv32", 4);
        else
                seq_write(f, "rv64", 4);
 
-       for (i = 0; i < sizeof(base_riscv_exts); i++) {
-               if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
-                       /* Print only enabled the base ISA extensions */
-                       seq_write(f, &base_riscv_exts[i], 1);
+       for (int i = 0; i < riscv_isa_ext_count; i++) {
+               if (!__riscv_isa_extension_available(NULL, riscv_isa_ext[i].id))
+                       continue;
+
+               /* Only multi-letter extensions are split by underscores */
+               if (strnlen(riscv_isa_ext[i].name, 2) != 1)
+                       seq_puts(f, "_");
+
+               seq_printf(f, "%s", riscv_isa_ext[i].name);
        }
-       print_isa_ext(f);
+
        seq_puts(f, "\n");
 }
 

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 859e383..d6009bd 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -144,6 +144,19 @@ static bool riscv_isa_extension_check(int id)
  * New entries to this struct should follow the ordering rules described above.
  */
 const struct riscv_isa_ext_data riscv_isa_ext[] = {
+       __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
+       __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
+       __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a),
+       __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
+       __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
+       __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
+       __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
+       __RISCV_ISA_EXT_DATA(b, RISCV_ISA_EXT_b),
+       __RISCV_ISA_EXT_DATA(k, RISCV_ISA_EXT_k),
+       __RISCV_ISA_EXT_DATA(j, RISCV_ISA_EXT_j),
+       __RISCV_ISA_EXT_DATA(p, RISCV_ISA_EXT_p),
+       __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
+       __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
        __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
        __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
        __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),