ret <4 x i32> %r
}
+define i32 @sub_lshr(i32 %x) {
+; CHECK-LABEL: sub_lshr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #43
+; CHECK-NEXT: sub w0, w8, w0, lsr #31
+; CHECK-NEXT: ret
+ %sh = lshr i32 %x, 31
+ %r = sub i32 43, %sh
+ ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: sub_lshr_vec_splat:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushr v0.4s, v0.4s, #31
+; CHECK-NEXT: movi v1.4s, #42
+; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+ ret <4 x i32> %r
+}
+
ret <4 x i32> %r
}
+define i32 @sub_lshr(i32 %x) {
+; CHECK-LABEL: sub_lshr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: srwi 3, 3, 31
+; CHECK-NEXT: subfic 3, 3, 43
+; CHECK-NEXT: blr
+ %sh = lshr i32 %x, 31
+ %r = sub i32 43, %sh
+ ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: sub_lshr_vec_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vspltisw 3, -16
+; CHECK-NEXT: vspltisw 4, 15
+; CHECK-NEXT: addis 3, 2, .LCPI19_0@toc@ha
+; CHECK-NEXT: addi 3, 3, .LCPI19_0@toc@l
+; CHECK-NEXT: vsubuwm 3, 4, 3
+; CHECK-NEXT: vsrw 2, 2, 3
+; CHECK-NEXT: lvx 3, 0, 3
+; CHECK-NEXT: vsubuwm 2, 3, 2
+; CHECK-NEXT: blr
+ %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+ ret <4 x i32> %r
+}
+
ret <4 x i32> %r
}
+define i32 @sub_lshr(i32 %x) {
+; CHECK-LABEL: sub_lshr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: shrl $31, %edi
+; CHECK-NEXT: xorl $43, %edi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: retq
+ %sh = lshr i32 %x, 31
+ %r = sub i32 43, %sh
+ ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: sub_lshr_vec_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psrld $31, %xmm0
+; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [42,42,42,42]
+; CHECK-NEXT: psubd %xmm0, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: retq
+ %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+ ret <4 x i32> %r
+}
+