drm/amdgpu: Enable SDMA MGCG for Vangogh
authorJinzhou Su <Jinzhou.Su@amd.com>
Wed, 21 Apr 2021 02:59:13 +0000 (10:59 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 23 Apr 2021 21:15:39 +0000 (17:15 -0400)
Add flags AMD_CG_SUPPORT_SDMA_MGCG for Vangogh.
Start to open sdma mgcg from firmware version 70.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

index d54af7f8801bf8f555a43d7d3622def657acb009..0142f6760ad20edfd0cf5092477b1fba8295aa72 100644 (file)
@@ -1118,6 +1118,7 @@ static int nv_common_early_init(void *handle)
                        AMD_CG_SUPPORT_MC_LS |
                        AMD_CG_SUPPORT_GFX_FGCG |
                        AMD_CG_SUPPORT_VCN_MGCG |
+                       AMD_CG_SUPPORT_SDMA_MGCG |
                        AMD_CG_SUPPORT_JPEG_MGCG;
                adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
                        AMD_PG_SUPPORT_VCN |
index b1ad9e52b2347e7c0d2e082a749b906acfe9bc4c..4ba7fce4c0b430e24435a92cbffd0f78ef927691 100644 (file)
@@ -1556,6 +1556,10 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
        int i;
 
        for (i = 0; i < adev->sdma.num_instances; i++) {
+
+               if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
+                       adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
+
                if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
                        /* Enable sdma clock gating */
                        def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));