RISC-V: Enable TARGET_SUPPORTS_WIDE_INT

This is at par with other major arches such as aarch64, i386, s390 ...

gcc/ChangeLog

	* config/riscv/predicates.md (const_0_operand): Remove
	const_double.
	* config/riscv/riscv.cc (riscv_rtx_costs): Add check for
	CONST_DOUBLE.
	* config/riscv/riscv.h (TARGET_SUPPORTS_WIDE_INT): New define.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 97cdbdf..40c1c72 100644 (file)
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -52,7 +52,7 @@
        (match_test "INTVAL (op) + 1 != 0")))
 
 (define_predicate "const_0_operand"
-  (and (match_code "const_int,const_wide_int,const_double,const_vector")
+  (and (match_code "const_int,const_wide_int,const_vector")
        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 
 (define_predicate "reg_or_0_operand"

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee756aa..fb66214 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1797,6 +1797,12 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
     case SYMBOL_REF:
     case LABEL_REF:
     case CONST_DOUBLE:
+      /* With TARGET_SUPPORTS_WIDE_INT const int can't be in CONST_DOUBLE
+        rtl object. Weird recheck due to switch-case fall through above.  */
+      if (GET_CODE (x) == CONST_DOUBLE)
+       gcc_assert (GET_MODE (x) != VOIDmode);
+      /* Fall through.  */
+
     case CONST:
       if ((cost = riscv_const_insns (x)) > 0)
        {

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index b191606..5083a1c 100644 (file)
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1009,4 +1009,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 
+#define TARGET_SUPPORTS_WIDE_INT 1
+
 #endif /* ! GCC_RISCV_H */