rockchip: dts: rk3328: add ehci and ohci node and enable host0 port

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 01794ed..9920935 100644 (file)
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -43,3 +43,11 @@
        pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
        status = "okay";
 };
+
+&usb_host0_ehci {
+       status = "okay";
+};
+
+&usb_host0_ohci {
+       status = "okay";
+};

diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 8a98ee3..e1219c3 100644 (file)
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -446,6 +446,20 @@
                status = "disabled";
        };
 
+       usb_host0_ehci: usb@ff5c0000 {
+               compatible = "generic-ehci";
+               reg = <0x0 0xff5c0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       usb_host0_ohci: usb@ff5d0000 {
+               compatible = "generic-ohci";
+               reg = <0x0 0xff5d0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
        sdmmc_ext: rksdmmc@ff5f0000 {
                compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff5f0000 0x0 0x4000>;