#define COMP_DBG BIT(1)
#define COMP_INIT BIT(2) /* Driver initialization/halt/reset. */
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#define COMP_RECV BIT(3) /* Receive data path. */
#define COMP_SEND BIT(4) /* Send data path. */
#define COMP_IO BIT(5)
#define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
#endif /* RTL8169_DEBUG */
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/* Queue Select Value in TxDesc */
#define QSLT_BK 0x1
#define QSLT_BE 0x0
} tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
#endif
-
-
typedef struct _tx_desc_cmd_819x_usb {
/* DWORD 0 */
u16 Reserved0;
u32 Reserved8;
} tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
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typedef struct _tx_fwinfo_819x_usb {
/* DOWRD 0 */
u8 TxRate:7;
#define PHY_RSSI_SLID_WIN_MAX 100
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typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = 0x01,
WIRELESS_MODE_N_5G = 0x20
} WIRELESS_MODE;
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#define RTL_IOCTL_WPA_SUPPLICANT (SIOCIWFIRSTPRIV + 30)
typedef struct buffer {
unsigned char buf[0xff];
} rtl_reg_debug;
-
-
-
-
-
typedef struct _rt_9x_tx_rate_history {
u32 cck[4];
u32 ofdm[8];
u32 CurrentShowTxate;
} Stats;
-
/* Bandwidth Offset */
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
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typedef struct ChnlAccessSetting {
u16 SIFS_Timer;
u16 DIFS_Timer;
u8 ccktxbb_valuearray[8];
} ccktxbbgain_struct, *pccktxbbgain_struct;
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typedef struct _init_gain {
u8 xaagccore1;
u8 xbagccore1;
u8 cck_agc_rpt;
} phy_sts_cck_819xusb_t;
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struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
u8 reserved:4;
u8 rxsc:2;
short sens;
short max_sens;
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short up;
/* If 1, allow bad crc frame, reception in monitor mode */
short crcmon;
short tx_urb_index;
atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
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struct tasklet_struct irq_rx_tasklet;
struct urb *rxurb_task;
u32 LastRxDescTSFHigh;
u32 LastRxDescTSFLow;
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/* Rx Related variables */
u16 EarlyRxThreshold;
u32 ReceiveConfig;
void EnableHWSecurityConfig8192(struct net_device *dev);
void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
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#endif