sysreset: add support for socfpga sysreset

This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga
to a UCLASS_SYSRESET based dm driver.

A side effect is that gen5 and a10 can now select between cold and warm
reset.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 51d4ace..0fc1813 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -895,10 +895,14 @@ config ARCH_SOCFPGA
        select SPL_OF_CONTROL
        select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
        select SPL_SERIAL_SUPPORT
+       select SPL_SYSRESET
        select SPL_WATCHDOG_SUPPORT
        select SUPPORT_SPL
        select SYS_NS16550
        select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+       select SYSRESET
+       select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+       select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10
        imply CMD_DM
        imply CMD_MTDPARTS
        imply CRC32_VERIFY

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e667204..fc1181c 100644 (file)
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,7 +8,6 @@
 obj-y  += board.o
 obj-y  += clock_manager.o
 obj-y  += misc.o
-obj-y  += reset_manager.o
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y  += clock_manager_gen5.o

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
deleted file mode 100644 (file)
index e0a01ed..0000000
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  Copyright (C) 2013 Altera Corporation <www.altera.com>
- */
-
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/reset_manager.h>
-
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include <asm/arch/mailbox_s10.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-static const struct socfpga_reset_manager *reset_manager_base =
-               (void *)SOCFPGA_RSTMGR_ADDRESS;
-#endif
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
-       /* request a warm reset */
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-       puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
-       mbox_reset_cold();
-#else
-       writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
-              &reset_manager_base->ctrl);
-#endif
-       /*
-        * infinite loop here as watchdog will trigger and reset
-        * the processor
-        */
-       while (1)
-               ;
-}

diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index ee4cbcb..822a3fe 100644 (file)
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -14,6 +14,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/lists.h>
 #include <dm/of_access.h>
 #include <reset-uclass.h>
 #include <linux/bitops.h>
@@ -130,6 +131,23 @@ static int socfpga_reset_remove(struct udevice *dev)
        return 0;
 }
 
+static int socfpga_reset_bind(struct udevice *dev)
+{
+       int ret;
+       struct udevice *sys_child;
+
+       /*
+        * The sysreset driver does not have a device node, so bind it here.
+        * Bind it to the node, too, so that it can get its base address.
+        */
+       ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
+                                        dev->node, &sys_child);
+       if (ret)
+               debug("Warning: No sysreset driver: ret=%d\n", ret);
+
+       return 0;
+}
+
 static const struct udevice_id socfpga_reset_match[] = {
        { .compatible = "altr,rst-mgr" },
        { /* sentinel */ },
@@ -139,6 +157,7 @@ U_BOOT_DRIVER(socfpga_reset) = {
        .name = "socfpga-reset",
        .id = UCLASS_RESET,
        .of_match = socfpga_reset_match,
+       .bind = socfpga_reset_bind,
        .probe = socfpga_reset_probe,
        .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
        .ops = &socfpga_reset_ops,