ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
+
+ /* ANV_PIPE_HDC_PIPELINE_FLUSH_BIT is a precise way to ensure prior data
+ * cache work has completed. Available on Gfx12+. For earlier Gfx we
+ * must reinterpret this flush as ANV_PIPE_DATA_CACHE_FLUSH_BIT.
+ */
+ ANV_PIPE_HDC_PIPELINE_FLUSH_BIT = (1 << 14),
ANV_PIPE_CS_STALL_BIT = (1 << 20),
ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),
fputs("+depth_flush ", stderr);
if (bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT)
fputs("+dc_flush ", stderr);
+ if (bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT)
+ fputs("+hdc_flush ", stderr);
if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
fputs("+rt_flush ", stderr);
if (bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT)
bits |= (pc->DCFlushEnable) ? ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0;
#if GFX_VER >= 12
bits |= (pc->TileCacheFlushEnable) ? ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0;
+ bits |= (pc->HDCPipelineFlushEnable) ? ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0;
#endif
bits |= (pc->RenderTargetCacheFlushEnable) ? ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT : 0;
bits |= (pc->StateCacheInvalidationEnable) ? ANV_PIPE_STATE_CACHE_INVALIDATE_BIT : 0;