vendor 41
end cpu cortex-m55
+begin cpu star-mc1
+ cname starmc1
+ tune flags LDSCHED
+ architecture armv8-m.main+dsp+fp
+ option nofp remove ALL_FP
+ option nodsp remove armv7em
+ isa quirk_no_asmcpu quirk_vlldm
+ costs v7m
+end cpu star-mc1
+
# V8 R-profile implementations.
begin cpu cortex-r52
cname cortexr52
cortexa710,cortexx1,neoversen1,
cortexa75cortexa55,cortexa76cortexa55,neoversev1,
neoversen2,cortexm23,cortexm33,
- cortexm35p,cortexm55,cortexr52,
- cortexr52plus"
+ cortexm35p,cortexm55,starmc1,
+ cortexr52,cortexr52plus"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
@samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
@samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale},
@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626},
-@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
+@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{star-mc1},
+@samp{xgene1}.
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible names are:
Mitigate against a potential security issue with the @code{VLLDM} instruction
in some M-profile devices when using CMSE (CVE-2021-365465). This option is
enabled by default when the option @option{-mcpu=} is used with
-@code{cortex-m33}, @code{cortex-m35p} or @code{cortex-m55}. The option
-@option{-mno-fix-cmse-cve-2021-35465} can be used to disable the mitigation.
+@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55} or @code{star-mc1}.
+The option @option{-mno-fix-cmse-cve-2021-35465} can be used to disable
+the mitigation.
@item -mstack-protector-guard=@var{guard}
@itemx -mstack-protector-guard-offset=@var{offset}