drm/i915: add WRPLL divider programming bits
authorEugeni Dodonov <eugeni.dodonov@intel.com>
Fri, 13 Apr 2012 20:08:38 +0000 (17:08 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 17 Apr 2012 09:50:49 +0000 (11:50 +0200)
Those are used to program the WRPLL dividers correctly for each gives
frequency.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h

index bc1a5c6..0668815 100644 (file)
 #define  WRPLL_PLL_SELECT_SSC                  (0x01<<28)
 #define  WRPLL_PLL_SELECT_NON_SCC              (0x02<<28)
 #define  WRPLL_PLL_SELECT_LCPLL_2700   (0x03<<28)
+/* WRPLL divider programming */
+#define  WRPLL_DIVIDER_REFERENCE(x)            ((x)<<0)
+#define  WRPLL_DIVIDER_POST(x)                 ((x)<<8)
+#define  WRPLL_DIVIDER_FEEDBACK(x)             ((x)<<16)
 
 /* Port clock selection */
 #define PORT_CLK_SEL_A                 0x46100