arm64/sysreg: Convert ID_AA64PFR1_EL1 to automatic generation

Convert ID_AA64PFR1_EL1 to be automatically generated as per DDI04187H.a,
no functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-26-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 2f032ea..e78d9dc 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -190,8 +190,6 @@
 #define SYS_MVFR1_EL1                  sys_reg(3, 0, 0, 3, 1)
 #define SYS_MVFR2_EL1                  sys_reg(3, 0, 0, 3, 2)
 
-#define SYS_ID_AA64PFR1_EL1            sys_reg(3, 0, 0, 4, 1)
-
 #define SYS_ID_AA64DFR0_EL1            sys_reg(3, 0, 0, 5, 0)
 #define SYS_ID_AA64DFR1_EL1            sys_reg(3, 0, 0, 5, 1)
 
@@ -683,25 +681,6 @@
 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY         0x1
 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT                0x2
 
-/* id_aa64pfr1 */
-#define ID_AA64PFR1_EL1_SME_SHIFT      24
-#define ID_AA64PFR1_EL1_MPAM_frac_SHIFT        16
-#define ID_AA64PFR1_EL1_RAS_frac_SHIFT 12
-#define ID_AA64PFR1_EL1_MTE_SHIFT      8
-#define ID_AA64PFR1_EL1_SSBS_SHIFT     4
-#define ID_AA64PFR1_EL1_BT_SHIFT       0
-
-#define ID_AA64PFR1_EL1_SSBS_NI                0
-#define ID_AA64PFR1_EL1_SSBS_IMP       1
-#define ID_AA64PFR1_EL1_SSBS_SSBS2     2
-#define ID_AA64PFR1_EL1_BT_IMP         0x1
-#define ID_AA64PFR1_EL1_SME_IMP                1
-
-#define ID_AA64PFR1_EL1_MTE_NI         0x0
-#define ID_AA64PFR1_EL1_MTE_IMP                0x1
-#define ID_AA64PFR1_EL1_MTE_MTE2       0x2
-#define ID_AA64PFR1_EL1_MTE_MTE3       0x3
-
 /* id_aa64mmfr0 */
 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN  0x0
 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX  0x7

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index e0b9903..ca821f9 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -122,6 +122,51 @@ Enum       3:0     EL0
 EndEnum
 EndSysreg
 
+Sysreg ID_AA64PFR1_EL1 3       0       0       4       1
+Res0   63:40
+Enum   39:36   NMI
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   35:32   CSV2_frac
+       0b0000  NI
+       0b0001  CSV2_1p1
+       0b0010  CSV2_1p2
+EndEnum
+Enum   31:28   RNDR_trap
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   SME
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Res0   23:20
+Enum   19:16   MPAM_frac
+       0b0000  MINOR_0
+       0b0001  MINOR_1
+EndEnum
+Enum   15:12   RAS_frac
+       0b0000  NI
+       0b0001  RASv1p1
+EndEnum
+Enum   11:8    MTE
+       0b0000  NI
+       0b0001  IMP
+       0b0010  MTE2
+       0b0011  MTE3
+EndEnum
+Enum   7:4     SSBS
+       0b0000  NI
+       0b0001  IMP
+       0b0010  SSBS2
+EndEnum
+Enum   3:0     BT
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
 Sysreg ID_AA64ZFR0_EL1 3       0       0       4       4
 Res0   63:60
 Enum   59:56   F64MM