i965: Add a flag for instructions with normal writemasking disabled.

For getting values from the new timestamp register, the channels we
load have nothing to do with the pixels dispatched.

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 00ba334..903d7ed 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -175,6 +175,7 @@ public:
    bool shadow_compare;
    bool force_uncompressed;
    bool force_sechalf;
+   bool force_writemask_all;
    uint32_t offset; /* spill/unspill offset */
 
    /** @{

diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 37eed1b..87a7e9b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -916,6 +916,7 @@ fs_generator::generate_code(exec_list *instructions)
       brw_set_predicate_control(p, inst->predicate);
       brw_set_predicate_inverse(p, inst->predicate_inverse);
       brw_set_saturate(p, inst->saturate);
+      brw_set_mask_control(p, inst->force_writemask_all);
 
       if (inst->force_uncompressed || dispatch_width == 8) {
         brw_set_compression_control(p, BRW_COMPRESSION_NONE);

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index d060941..8c6f56a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -171,6 +171,7 @@ public:
    src_reg src[3];
 
    bool saturate;
+   bool force_writemask_all;
 
    int conditional_mod; /**< BRW_CONDITIONAL_* */
 

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 7609d92..0c6b358 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -723,6 +723,7 @@ vec4_generator::generate_code(exec_list *instructions)
       brw_set_predicate_control(p, inst->predicate);
       brw_set_predicate_inverse(p, inst->predicate_inverse);
       brw_set_saturate(p, inst->saturate);
+      brw_set_mask_control(p, inst->force_writemask_all);
 
       switch (inst->opcode) {
       case BRW_OPCODE_MOV: