drm/i915: Move power well get/put/enable/disable functions to a new file

Move the power well get/put/enable/disable hooks to the new
intel_display_power_well.c file. The motivation is to reduce the clutter
in intel_display_power.c, keeping the functionality related to power
domains in that file and moving the low-level power well functionality
to intel_display_power_well.c.

No functional change.

Suggested-by: Jani Nikula <jani.nikula@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220222165137.1004194-6-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9d588d9..1a771ee 100644 (file)
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -212,6 +212,7 @@ i915-y += \
        display/intel_cursor.o \
        display/intel_display.o \
        display/intel_display_power.o \
+       display/intel_display_power_well.o \
        display/intel_dmc.o \
        display/intel_dpio_phy.o \
        display/intel_dpll.o \

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 32e4fc6..a18895a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -11,6 +11,7 @@
 #include "intel_crt.h"
 #include "intel_de.h"
 #include "intel_display_power.h"
+#include "intel_display_power_well.h"
 #include "intel_display_types.h"
 #include "intel_dmc.h"
 #include "intel_dpio_phy.h"
@@ -26,98 +27,6 @@
 #include "intel_vga.h"
 #include "vlv_sideband.h"
 
-struct i915_power_well_regs {
-       i915_reg_t bios;
-       i915_reg_t driver;
-       i915_reg_t kvmr;
-       i915_reg_t debug;
-};
-
-struct i915_power_well_ops {
-       const struct i915_power_well_regs *regs;
-       /*
-        * Synchronize the well's hw state to match the current sw state, for
-        * example enable/disable it based on the current refcount. Called
-        * during driver init and resume time, possibly after first calling
-        * the enable/disable handlers.
-        */
-       void (*sync_hw)(struct drm_i915_private *dev_priv,
-                       struct i915_power_well *power_well);
-       /*
-        * Enable the well and resources that depend on it (for example
-        * interrupts located on the well). Called after the 0->1 refcount
-        * transition.
-        */
-       void (*enable)(struct drm_i915_private *dev_priv,
-                      struct i915_power_well *power_well);
-       /*
-        * Disable the well and resources that depend on it. Called after
-        * the 1->0 refcount transition.
-        */
-       void (*disable)(struct drm_i915_private *dev_priv,
-                       struct i915_power_well *power_well);
-       /* Returns the hw enabled state. */
-       bool (*is_enabled)(struct drm_i915_private *dev_priv,
-                          struct i915_power_well *power_well);
-};
-
-/* Power well structure for haswell */
-struct i915_power_well_desc {
-       const char *name;
-       bool always_on;
-       u64 domains;
-       /* unique identifier for this power well */
-       enum i915_power_well_id id;
-       /*
-        * Arbitraty data associated with this power well. Platform and power
-        * well specific.
-        */
-       union {
-               struct {
-                       /*
-                        * request/status flag index in the PUNIT power well
-                        * control/status registers.
-                        */
-                       u8 idx;
-               } vlv;
-               struct {
-                       enum dpio_phy phy;
-               } bxt;
-               struct {
-                       /*
-                        * request/status flag index in the power well
-                        * constrol/status registers.
-                        */
-                       u8 idx;
-                       /* Mask of pipes whose IRQ logic is backed by the pw */
-                       u8 irq_pipe_mask;
-                       /*
-                        * Instead of waiting for the status bit to ack enables,
-                        * just wait a specific amount of time and then consider
-                        * the well enabled.
-                        */
-                       u16 fixed_enable_delay;
-                       /* The pw is backing the VGA functionality */
-                       bool has_vga:1;
-                       bool has_fuses:1;
-                       /*
-                        * The pw is for an ICL+ TypeC PHY port in
-                        * Thunderbolt mode.
-                        */
-                       bool is_tc_tbt:1;
-               } hsw;
-       };
-       const struct i915_power_well_ops *ops;
-};
-
-struct i915_power_well {
-       const struct i915_power_well_desc *desc;
-       /* power well enable/disable usage count */
-       int count;
-       /* cached hw enabled state */
-       bool hw_enabled;
-};
-
 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
                                         enum i915_power_well_id power_well_id);
 
@@ -259,40 +168,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
        }
 }
 
-static void intel_power_well_enable(struct drm_i915_private *dev_priv,
-                                   struct i915_power_well *power_well)
-{
-       drm_dbg_kms(&dev_priv->drm, "enabling %s\n", power_well->desc->name);
-       power_well->desc->ops->enable(dev_priv, power_well);
-       power_well->hw_enabled = true;
-}
-
-static void intel_power_well_disable(struct drm_i915_private *dev_priv,
-                                    struct i915_power_well *power_well)
-{
-       drm_dbg_kms(&dev_priv->drm, "disabling %s\n", power_well->desc->name);
-       power_well->hw_enabled = false;
-       power_well->desc->ops->disable(dev_priv, power_well);
-}
-
-static void intel_power_well_get(struct drm_i915_private *dev_priv,
-                                struct i915_power_well *power_well)
-{
-       if (!power_well->count++)
-               intel_power_well_enable(dev_priv, power_well);
-}
-
-static void intel_power_well_put(struct drm_i915_private *dev_priv,
-                                struct i915_power_well *power_well)
-{
-       drm_WARN(&dev_priv->drm, !power_well->count,
-                "Use count on power well %s is already zero",
-                power_well->desc->name);
-
-       if (!--power_well->count)
-               intel_power_well_disable(dev_priv, power_well);
-}
-
 /**
  * __intel_display_power_is_enabled - unlocked check for a power domain
  * @dev_priv: i915 device instance

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
new file mode 100644 (file)
index 0000000..e211908
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_display_power_well.h"
+
+void intel_power_well_enable(struct drm_i915_private *i915,
+                            struct i915_power_well *power_well)
+{
+       drm_dbg_kms(&i915->drm, "enabling %s\n", power_well->desc->name);
+       power_well->desc->ops->enable(i915, power_well);
+       power_well->hw_enabled = true;
+}
+
+void intel_power_well_disable(struct drm_i915_private *i915,
+                             struct i915_power_well *power_well)
+{
+       drm_dbg_kms(&i915->drm, "disabling %s\n", power_well->desc->name);
+       power_well->hw_enabled = false;
+       power_well->desc->ops->disable(i915, power_well);
+}
+
+void intel_power_well_get(struct drm_i915_private *i915,
+                         struct i915_power_well *power_well)
+{
+       if (!power_well->count++)
+               intel_power_well_enable(i915, power_well);
+}
+
+void intel_power_well_put(struct drm_i915_private *i915,
+                         struct i915_power_well *power_well)
+{
+       drm_WARN(&i915->drm, !power_well->count,
+                "Use count on power well %s is already zero",
+                power_well->desc->name);
+
+       if (!--power_well->count)
+               intel_power_well_disable(i915, power_well);
+}

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
new file mode 100644 (file)
index 0000000..bc77de3
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+#ifndef __INTEL_DISPLAY_POWER_WELL_H__
+#define __INTEL_DISPLAY_POWER_WELL_H__
+
+#include <linux/types.h>
+
+#include "intel_display.h"
+#include "intel_display_power.h"
+
+struct drm_i915_private;
+
+struct i915_power_well_regs {
+       i915_reg_t bios;
+       i915_reg_t driver;
+       i915_reg_t kvmr;
+       i915_reg_t debug;
+};
+
+struct i915_power_well_ops {
+       const struct i915_power_well_regs *regs;
+       /*
+        * Synchronize the well's hw state to match the current sw state, for
+        * example enable/disable it based on the current refcount. Called
+        * during driver init and resume time, possibly after first calling
+        * the enable/disable handlers.
+        */
+       void (*sync_hw)(struct drm_i915_private *i915,
+                       struct i915_power_well *power_well);
+       /*
+        * Enable the well and resources that depend on it (for example
+        * interrupts located on the well). Called after the 0->1 refcount
+        * transition.
+        */
+       void (*enable)(struct drm_i915_private *i915,
+                      struct i915_power_well *power_well);
+       /*
+        * Disable the well and resources that depend on it. Called after
+        * the 1->0 refcount transition.
+        */
+       void (*disable)(struct drm_i915_private *i915,
+                       struct i915_power_well *power_well);
+       /* Returns the hw enabled state. */
+       bool (*is_enabled)(struct drm_i915_private *i915,
+                          struct i915_power_well *power_well);
+};
+
+struct i915_power_well_desc {
+       const char *name;
+       bool always_on;
+       u64 domains;
+       /* unique identifier for this power well */
+       enum i915_power_well_id id;
+       /*
+        * Arbitraty data associated with this power well. Platform and power
+        * well specific.
+        */
+       union {
+               struct {
+                       /*
+                        * request/status flag index in the PUNIT power well
+                        * control/status registers.
+                        */
+                       u8 idx;
+               } vlv;
+               struct {
+                       enum dpio_phy phy;
+               } bxt;
+               struct {
+                       /*
+                        * request/status flag index in the power well
+                        * constrol/status registers.
+                        */
+                       u8 idx;
+                       /* Mask of pipes whose IRQ logic is backed by the pw */
+                       u8 irq_pipe_mask;
+                       /*
+                        * Instead of waiting for the status bit to ack enables,
+                        * just wait a specific amount of time and then consider
+                        * the well enabled.
+                        */
+                       u16 fixed_enable_delay;
+                       /* The pw is backing the VGA functionality */
+                       bool has_vga:1;
+                       bool has_fuses:1;
+                       /*
+                        * The pw is for an ICL+ TypeC PHY port in
+                        * Thunderbolt mode.
+                        */
+                       bool is_tc_tbt:1;
+               } hsw;
+       };
+       const struct i915_power_well_ops *ops;
+};
+
+struct i915_power_well {
+       const struct i915_power_well_desc *desc;
+       /* power well enable/disable usage count */
+       int count;
+       /* cached hw enabled state */
+       bool hw_enabled;
+};
+
+void intel_power_well_enable(struct drm_i915_private *i915,
+                            struct i915_power_well *power_well);
+void intel_power_well_disable(struct drm_i915_private *i915,
+                             struct i915_power_well *power_well);
+void intel_power_well_get(struct drm_i915_private *i915,
+                         struct i915_power_well *power_well);
+void intel_power_well_put(struct drm_i915_private *i915,
+                         struct i915_power_well *power_well);
+
+#endif