clk: renesas: Add r8a774e1 CPG Core Clock Definitions

Add all RZ/G2H Clock Pulse Generator Core Clock Outputs, as listed in
Table 11.2 ("List of Clocks [RZ/G2H]") of the RZ/G2H Hardware User's
Manual.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594138692-16816-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h
new file mode 100644 (file)
index 0000000..b2fc1d1
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R8A774E1 CPG Core Clocks */
+#define R8A774E1_CLK_Z                 0
+#define R8A774E1_CLK_Z2                        1
+#define R8A774E1_CLK_ZG                        2
+#define R8A774E1_CLK_ZTR               3
+#define R8A774E1_CLK_ZTRD2             4
+#define R8A774E1_CLK_ZT                        5
+#define R8A774E1_CLK_ZX                        6
+#define R8A774E1_CLK_S0D1              7
+#define R8A774E1_CLK_S0D2              8
+#define R8A774E1_CLK_S0D3              9
+#define R8A774E1_CLK_S0D4              10
+#define R8A774E1_CLK_S0D6              11
+#define R8A774E1_CLK_S0D8              12
+#define R8A774E1_CLK_S0D12             13
+#define R8A774E1_CLK_S1D2              14
+#define R8A774E1_CLK_S1D4              15
+#define R8A774E1_CLK_S2D1              16
+#define R8A774E1_CLK_S2D2              17
+#define R8A774E1_CLK_S2D4              18
+#define R8A774E1_CLK_S3D1              19
+#define R8A774E1_CLK_S3D2              20
+#define R8A774E1_CLK_S3D4              21
+#define R8A774E1_CLK_LB                        22
+#define R8A774E1_CLK_CL                        23
+#define R8A774E1_CLK_ZB3               24
+#define R8A774E1_CLK_ZB3D2             25
+#define R8A774E1_CLK_ZB3D4             26
+#define R8A774E1_CLK_CR                        27
+#define R8A774E1_CLK_CRD2              28
+#define R8A774E1_CLK_SD0H              29
+#define R8A774E1_CLK_SD0               30
+#define R8A774E1_CLK_SD1H              31
+#define R8A774E1_CLK_SD1               32
+#define R8A774E1_CLK_SD2H              33
+#define R8A774E1_CLK_SD2               34
+#define R8A774E1_CLK_SD3H              35
+#define R8A774E1_CLK_SD3               36
+#define R8A774E1_CLK_RPC               37
+#define R8A774E1_CLK_RPCD2             38
+#define R8A774E1_CLK_MSO               39
+#define R8A774E1_CLK_HDMI              40
+#define R8A774E1_CLK_CSI0              41
+#define R8A774E1_CLK_CP                        42
+#define R8A774E1_CLK_CPEX              43
+#define R8A774E1_CLK_R                 44
+#define R8A774E1_CLK_OSC               45
+#define R8A774E1_CLK_CANFD             46
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */